peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 302

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

SSF…
SRFSO…
Line Interface Mode 3 (Read/Write)
Value after RESET: 00
CSC…
Data Sheet
LIM3
7
started again. The freeze signaling status could be also automatically
generated by detecting the Loss of Signal alarm or a Loss of Frame
Alignment or a receive slip (only if external register access via RSIG
is enabled). This automatic freeze signaling function is logically ored
with this bit.
The current internal freeze signaling status is available in register
SIS.SFS.
Serial Signaling Format
Only applicable if pin function R/XSIG is selected.
0…
1…
0…
1…
Setting this bit disables the timeslot assigner. With register RC1/0 the
receive frame marker could be activated during any bit position of the
current frame. This marker is active high for one 1.544-MHz cycle and
is clocked off with the falling edge of SCLKR or RCLK if the receive
elastic store is bypassed. If no SYPR has been activated since
RESET or software reset CMDR.RES the outputs of the receive
system interface assumes an arbitrary alignment.
Calculation of the value X of the “Receive Counter Offset” register
RC1/0 depends on SCLKR and on the bit position BP which should
be marked:
X = (2BP) mod 386, for SCLKR = 1.544 MHz
Configure System Clock CLK16M/CLK12M
0…
1…
Select Receive Frame Sync Output
H
Bits 1...4 in all time-slots except time-slot 0 + 16 are cleared.
Bits 1...4 in all time-slots except time-slot 0 + 16 are set high.
Dejittered XTAL1 or XTAL3 clock is output on CLK16M/
CLK12M.
Buffered XTAL1 or XTAL3 clock is output on CLK16M/
CLK12M.
Pin SYPR: Input
Pin SYPR: Output
302
CSC
FALC-LH V1.3
T1/J1 Registers
ESY
0
PEB 2255
2000-07
(3E)