peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 273

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RC1…0…
FRS…
SRAF…
EXLS…
SIM…
Data Sheet
10…AMI coding with Zero Code Suppression (ZCS, B7-Stuffing).
11…B8ZS Code (ternary or digital dual rail interface)
Serial code receiver is independent to the transmitter.
00… NRZ (optical interface)
01… Not assigned
10… AMI coding (ternary or digital dual rail interface)
11… B8ZS Code (ternary or digital dual rail interface)
Force Resynchronization
A transition from low to high forces the frame aligner to execute a
resynchronization of the pulse frame. In the asynchronous state, a
new frame position is assumed at the next candidate if there is one.
Otherwise, a new frame search with the meaning of a general reset is
started. In the synchronous state this bit has the same meaning as bit
FMR0.EXLS except if FMR2.MCSP=1. This bit is not reset
automatically.
0…
1…
External Loss Of Frame
With a low to high transition a new frame search is started. This has
the meaning of a general reset of the internal frame alignment unit.
Synchronous state is reached only if there is one definite framing
candidate. In the case of multiple candidates, the setting of the bit
FMR0.FRS forces the receiver to lock onto the next available framing
position. This bit is not reset automatically.
Alarm Simulation
Setting/resetting this bit initiates internal error simulation of: AIS (blue
alarm), loss of signal (red alarm), loss of frame alignment, remote
(yellow) alarm, slip, framing errors, CRC errors, code violations. The
error counters FEC, CVC, CEC, EBC are incremented.
The selection of simulated alarms is done via the error simulation
counter: FRS2.ESC2...0 which are incremented with each setting of
bit FMR0.SIM. For complete checking of the alarm indications eight
Receive Code
Select Remote (Yellow) Alarm Format for F12 and ESF Format
Disabling of the ZCS is done by activating the clear channel
mode via register CCB1...3. (ternary or digital interface)
F12: bit2 = 0 in every channel. ESF: pattern
‘1111 1111 0000 0000…’ in data link channel.
F12: FS bit of frame 12. ESF: bit2 = 0 in every channel
273
FALC-LH V1.3
T1/J1 Registers
PEB 2255
2000-07