peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 245

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Receive Sa6-Bit Status (Read)
S_X…
S_F…
S_E…
S_C…
Data Sheet
RSA6S
7
Four consecutive received SA6-bits are checked on the by ETS
300233 defined SA6-bit combinations. The FALC
following “fixed” SA6-bit combinations:
SA61,SA62,SA63,SA64=1000; 1010; 1100; 1110; 1111. All other
possible 4 bit combinations are grouped to status “X”.
A valid SA6-bit combination must occur three times in a row. The
corresponding status bit in this register is set. Even if the detected
status is active for a short time the status bit remains active until this
register is read. Reading the register resets all pending status
information.
With any change of state of the SA6-bit combinations an interrupt
status ISR0.SA6SC is generated.
During the basic frame asynchronous state updating of this register
and interrupt status ISR0.SA6SC is disabled. In multiframe format the
detection of the SA6-bit combinations can be done either
synchronous or asynchronous to the submultiframe (FMR3.SA6SY).
In synchronous detection mode updating of register RSA6S is done
in
asynchronous state detection mode updating is independent of the
multiframe synchronous state.
Receive S
If none of the fixed SA6-bit combinations are detected this bit is set.
Receive S
Receive SA6-bit status “1111” is detected for three times in a row in
the SA6-bit positions.
Receive S
Receive SA6-bit status “1110” is detected for three times in a row in
the SA6-bit positions.
Receive S
Receive SA6-bit status “1100” is detected for three times in a row in
the SA6-bit positions.
the
S_X
multiframe
a
a
a
a
6-Bit Status_X
6-Bit Status: “1111”
6-Bit Status: “1110”
6-Bit Status: “1100”
S_F
245
synchronous
S_E
S_C
state
S_A
(FRS0.LMFA=0).
®
FALC-LH V1.3
-LH detects the
S_8
E1 Registers
0
PEB 2255
2000-07
(61)
In