peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 37

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 4
Pin No.
65
63
Data Sheet
Symbol
SYPR
RFM
SCLKR
Pin Definitions - System Interface (cont’d)
Input (I)
Output (O)
Supply (S)
I
O
I
Function
Synchronous Pulse Receive
SIC2.SRFSO = 0 (reset value):
Defines the beginning of time slot 0 on system
highway port RDO together with the values of
RC0.RCO, RC0.RCOS and RC1.RTO.
Sampling is done with the falling edge of
SCLKR.
The pulse cycle is an integer multiple of 125 µs.
Receive Frame Marker
SIC2.SRFSO = 1:
This marker will be active high for one 2.048-
MHz (E1)/1.544-MHz (T1/J1) cycle (SIC1.SRSC
= 1; 2.048 Mbit/s PCM highway interface mode)
or two 8.192-MHz cycles (SIC1.SRSC = 0;
4.096 Mbit/s PCM highway interface mode). It is
clocked with the falling edge of SCLKR or RCLK,
depending on the selected receive buffer size
(SIC1).The marker can be activated within any
bit position of a received frame (RC0/1).
System Clock Receive
Working clock for the receive system interface
with a frequency of 8.192 MHz (SIC1.SRSC = 0,
SIC1.SXSC=0) or 2.048 MHz (E1)/1.544 MHz
(T1/J1) (SIC1.SRSC = 1, SIC1.SXSC=1). If the
receive elastic store is bypassed
(SIC1.RBS1...0), the clock supplied on this pin is
ignored. During reset phase, a clock has to be
provided.
37
Pin Descriptions
FALC-LH V1.3
PEB 2255
2000-07