peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 253

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 2 (Read)
All bits are reset when ISR2 is read.
If bit IPC.VIS is set, interrupt statuses in ISR2 may be flagged although they are masked
via register IMR2. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
FAR…
LFA…
MFAR…
T400MS…
AIS…
Data Sheet
ISR2
FAR
7
The framer has reached doubleframe synchronization. Set when bit
FSR0.LFA is reset. It is set also after alarm simulation is finished and
the receiver is still synchronous.
Loss of Frame Alignment
The framer has lost synchronization and bit FRS0.LFA is set. It is set
during alarm simulation.
Set when the framer has found two CRC-multiframes at an interval of
n
FRS0.LMFA is reset.
It is set also after alarm simulation is finished and the receiver is still
synchronous. Only active if CRC-multiframe format is selected.
Receive Time Out 400 msec
Only active if multiframing is enabled.
The
FRS0.LFA = 0 and is searching for the multiframing. This interrupt is
set to indicate that no multiframing could be found within a time
window of 400 ms after basic framing has been achieved. In
multiframe synchronous state this interrupt is not generated.
Alarm Indication Signal
This bit is set when an alarm indication signal is detected and bit
FRS0.AIS is set. It is set during alarm simulation.
If IPC.SCI is set high this interrupt status bit is set with every change
of state of FRS0.AIS.
Frame Alignment Recovery
Multiframe Alignment Recovery
LFA
2 ms (n = 1, 2, 3, …) without a framing error. At the same time bit
framer
MFAR T400MS
has
found
253
AIS
the
doubleframing
LOS
RAR
FALC-LH V1.3
(basic
RA
E1 Registers
0
PEB 2255
framing)
2000-07
(6A)