peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 130

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

PEB 2255
FALC-LH V1.3
Functional Description T1/J1
ignored. The FS/DL bit is sampled on port XSIG and inserted in the outgoing data
stream. The received CAS multiframe is inserted frame aligned into the data stream on
XDI. Data sourced by the internal signaling controller overwrites the external signaling
data.
Internal multiplexing of data and signaling data may be disabled on a per time slot basis
(Clear Channel Capability). This is also valid when using the internal and external
signaling mode.
5.3.1.3
Data Link Access in ESF/F24 and F72 Format (T1/J1)
The DL-channel protocol is supported as follows:
- access is done on a multiframe basis via registers XDL1-3 or
- HDLC access or transparent transmission (non HDLC mode) from XFIFO
The signaling information stored in the XFIFO is inserted in the DL bits of frame 26 to 72
in F72 format or in every other frame in ESF format. Operating in HDLC or BOM mode
“flags” or “idle” may be transmitted as interframe timefill.
Data Sheet
130
2000-07