peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 101

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

PEB 2255
FALC-LH V1.3
Functional Description E1
4.6.6
Alarm Simulation (E1)
Alarm simulation does not affect the normal operation of the device, i.e. all time slots
remain available for transmission. However, possible ‘real’ alarm conditions are not
reported to the processor when the device is in the alarm simulation mode.
The alarm simulation is initiated by setting the bit FMR0.SIM. The following alarms are
simulated:
• Loss of Signal
• Alarm Indication Signal (AIS)
• Loss of pulse frame
• Remote alarm indication
• Receive and transmit slip indication
• Framing error counter
• Code violation counter (HDB3 Code)
• CRC4 error counter
• E-Bit error counter
• CEC2 counter
• CEC3 counter
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Some of the above indications are only simulated if the FALC
-LH is configured in a
mode where the alarm is applicable (e.g. no CRC4 error simulation when doubleframe
format is enabled).
Setting of the bit FMR0.SIM initiates alarm simulation, interrupt status bits is set. Error
counting and indication occurs while this bit is set. After it is reset all simulated error
conditions disappear, but the generated interrupt statuses are still pending until the
corresponding interrupt status register is read. Alarms like AIS and LOS are cleared
automatically. Interrupt status register and error counters are automatically cleared on
read.
Data Sheet
101
2000-07