peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 79

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

• Auxiliary pattern generation
The frame/multiframe boundaries of the transmitter may be externally synchronized by
using the SYPX/XMFS pin. Any change of the transmit time slot assignment
subsequently produces a change of the framing bit positions on the line side. This
feature is required if signaling- and service- bits are routed through the switching network
and are inserted in transmit direction via the system interface.
In loop-timed configuration (LIM2.ELT) disconnecting the control of the transmit system
highway from the transmitter is done by setting XSW.XTM. The transmitter is now in a
free running mode without any possibility to update the multiframe position in case of
changing the transmit time slot assignment. The framing bits are generated independent
of the transmit system interface. For proper operation the transmit elastic buffer size
should be programmed to 2 frames.
The contents of selectable time slots can be overwritten by the pattern defined via
register IDLE. The selection of “idle channels” is done by programming the four-byte
registers ICB1 … ICB4.
4.3.4
The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar)
return to zero signals of the appropriate programmable shape. The unipolar data is
provided by the digital transmitter.
Figure 23
•
Table 16
Parameter
R
t2 : t1
1)
Data Sheet
1
includes all parasitics
( 1 %) [ ]
1)
Transmit Line Interface (E1)
Transmitter Configuration (E1)
Example Transmitter Configuration Values (E1)
Line
t
1
t
2
79
R
R
1
1
Characteristic Impedance [ ]
1 :
XL1
XL2
120
18
FALC
2
Functional Description E1
R
ITS10968
FALC-LH V1.3
1 :
PEB 2255
75
18
2
2000-07