peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 203

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

XS15…
Transmit Control 0 (Read/Write)
Value after RESET: 00
SA8E...4E
XCO2...0…
Transmit Control 1 (Read/Write)
Value after RESET: 00
Data Sheet
A write access to this address resets the transmit elastic buffer to its basic starting
position. Therefore, updating the value should only be done when the FALC
XC0
XC1
XCOS
SA8E
7
7
Transmit Spare Bit (Frame 15, CRC-Multiframe)
First bit in the service word of frame 15 for international use. Only
significant in CRC-multiframe format. If not used, this bit should be
fixed to ‘1’. The information of XSP.XS15 is shifted into internal
transmission buffer with beginning of the next following transmitted
CRC multiframe.
If automatic transmission of submultiframe status is enabled via bit
XSP.AXS, or, if one of the time slot 0 transparent modes XSP.TT0 or
TSWM.TSIF is enabled, bit XSP.XS15 is ignored.
SA Bit Signaling Enable
0…
1…
Transmit Clock Slot Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX is active. Refer to
register XC1. XCO0 must be cleared if SIC1.SXSC is set.
SA7E
H
H
Standard operation.
By setting this bit it is possible to send/receive a LAPD protocol
in any combination of the SA8...SA4 bit positions in the
outgoing/incoming data stream. The on chip signaling
controller has to be configured in the HDLC/LAPD mode. In
transmit direction together with these bits the TSWM.TSA8-4
bits must be set to enable transmission to the remote end
transparently through the FALC
SA6E
XTO5
SA5E
XTO4
203
SA4E
XTO3
XCO2
XTO2
®
-LH.
XCO1
XTO1
FALC-LH V1.3
XCO0
XTO0
E1 Registers
0
0
PEB 2255
®
2000-07
(20)
(21)
-LH is