peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 138

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

and FRS0.LMFA SSP = 1:FT
FS
ESF:ESF framing bits
The resynchronization procedure may be controlled by either one of the following
procedure:
• Automatically (FMR4.AUTO = 1). Additionally, it may be triggered by the user by
• User controlled, exclusively, via above control bits in the non-auto-mode
FT and FS bit conditions, i.e. pulse frame alignment and multiframe alignment can be
handled separately if programmed via bit FMR2.SSP. Thus, a multiframe re-
synchronization can be automatically initiated after detecting 2 errors out of 4/5/6
consecutive multiframing bits without influencing the state of the terminal framing.
In the synchronous state, the setting of FMR0.FRS or FMR0.EXLS resets the
synchronizer and initiates a new frame search. The synchronous state is reached if there
is only one definite framing candidate. In the case of repeated apparent simulated
candidates, the synchronizer remains in the asynchronous state.
In asynchronous state, the function of FMR0.EXLS is the same as above. Setting bit
FMR0.FRS induces the synchronizer to lock onto the next available framing candidate if
there is one. Otherwise, a new frame search is started. This is useful in case the framing
pattern that defines the pulseframe position is imitated periodically by a pattern in one of
the speech/data channels.
The control bit FMR0.EXLS should be used first because it starts the synchronizer to
search for a definite framing candidate.
To observe actions of the synchronizer, the Frame Search Restart Flag FRS0.FSRF is
implemented. It toggles at the start of a new frame search if no candidate has been found
at previous attempt.
When resynchronization is initiated, the following values apply for the time required to
achieve the synchronous state in case there is one definite framing candidate within the
data stream:
•
Table 32
Frame Mode
F4
F12
ESF
F72
Data Sheet
setting/resetting one of the bits FMR0.FRS (Force Resynchronization) or FMR0.EXLS
(External Loss of Frame).
(FMR4.AUTO = 0).
FRS0.LMFA
Resynchronization Timing (T1/J1)
Average
1.0
3.5
3.4
13.0
FRS0.LFA
FRS0.LFA
138
Maximum
1.5
4.5
6.125
17.75
Functional Description T1/J1
Units
ms
ms
ms
ms
FALC-LH V1.3
PEB 2255
2000-07