peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 123

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

PEB 2255
FALC-LH V1.3
Functional Description T1/J1
5.3
Transmit Path in T1/J1 Mode
Compared to the receive paths the inverse functions are performed for the transmit
direction.
The interface to the transmit system highway is realized by two data buses, one for the
data XDI and one for the signaling data XSIG. The time slot assignment is equivalent to
the receive direction. All unequipped (idle) time slots are ignored.
Latching of data is controlled by the System Clock (SCLKX) and the Synchronous Pulse
(SYPX/XMFS) in conjunction with the programmed offset values for the Transmit Time
slot/Clock slot Counters XC1/0. The frequency of the working clock for the transmit
system interface is programmable by SIC1.SXSC. Refer also to
Table 27
on page 117.
The received bit stream on ports XDI and XSIG can be multiplexed internally on a time
slot basis, if enabled by SIC3.TTRF = 1, if not serial CAS mode is selected (see
Chapter 5.1.12.2
on page 115). The data received on port XSIG can be sampled if the
transmit signaling marker XSIGM is active high. Data on port XDI is sampled if XSIGM
is low for the respective time slot. Programming the XSIGM marker is done with registers
TTR1-4.
Data Sheet
123
2000-07