peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 68

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

•
Figure 17
4.1.12.4 Channel Associated Signaling CAS (E1, µP access mode)
The signaling information is carried in time slot 16 (TS16). Receive data is stored in
registers RS1-16 aligned to the CAS multiframe boundary. The signaling controller
samples the bit stream on the receive line side.
The signaling procedure is done as it is described in ITU-T G.704 and G.732.
The main functions are:
• Synchronization to a CAS multiframe
• Detection of AIS and remote alarm in CAS multiframes
• Separation of CAS service bits
• Storing of received data in registers RS1...16 with last look capability
Updating of the receive signaling information is controlled by the freeze signaling status.
If signaling information is frozen updating of the registers RS1...16 is disabled. The
freeze signaling status is output on pin RFSP/FREEZS and is generated, if:
• Bit FRS1.TSL16LFA = 1
The receive signaling buffer is updated if the alarm remains inactive for at least one
complete CAS multiframe.
To relieve the µP load from always reading the complete RS1-16 buffer every 2 ms the
FALC
one multiframe to the next.
The CAS controller acts on the PCM highway side of the receive buffer. Therefore slips
disturb CAS data.
Data Sheet
SYPR
SCLKR
RDO
RSIG
®
-LH notifies the µP via interrupt ISR0.CASC only when signaling changes from
T
FAS
NFAS
ABCD
TS31
A
B
2.048 MHz Receive Signaling Highway (E1)
C
= Time-Slot Offset (Register RC1/0)
= Frame Alignment Signal
= TS0 not containing the FAS word
= Signaling Bits for Time-Slot 1-30 of CAS Multiframe
T
D
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FAS / NFAS
TS0
TS1
A B C D
125 s
68
Functional Description E1
0 1 2 3 4 5 6 7
TS31
FALC-LH V1.3
A
B
C
PEB 2255
D
ITT10517
2000-07