ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 99

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

www.national.com
down the SDA line during the acknowledge clock pulse,
thus signalling the correct reception of the last data byte,
and its readiness to receive the next byte. Figure 13-4 illus-
13.2.5 “Acknowledge after every byte” Rule
The master generates an acknowledge clock pulse after
each byte transfer. The receiver sends an acknowledge sig-
nal after every byte received.
There are two exceptions to the “acknowledge after every
byte” rule.
Receiver
Data Output
Transmitter
Data Output
SDA
SCL
SDA
SCL
Start
Condition
SCL
Start
Condition
S
S
Figure 13-5. A Complete ACCESS.bus Data Transaction
Start
Condition
S
MSB
Address R/W ACK
Figure 13-4. ACCESS.bus Acknowledge Cycle
1
1 - 7
Figure 13-3. ACCESS.bus Data Transaction
2 3 - 6
1
Interrupt Within
Byte Complete
8
2 3 - 6
ACCESS.bus (ACB) Interface
9
7
Receiver
8
7
1 - 7
ACK
Data
99
9
8
trates the acknowledge cycle.
1. When the master is the receiver, it must indicate to the
2. When the receiver is full, otherwise occupied, or a prob-
Acknowledgment
Signal From Receiver
9
8
transmitter an end of data by not-acknowledging (“neg-
ative acknowledge”) the last byte clocked out of the
slave. This “negative acknowledge” still includes the ac-
knowledge clock pulse (generated by the master), but
the SDA line is not pulled down.
1
ACK
Clock Line Held
Low by Receiver
While Interrupt
is Serviced
9
2
1 - 7
3 - 8
Data
Transmitter Stays Off the
Bus During the
Acknowledge Clock
Acknowledge
Signal from Receiver
ACK
9
8
ACK
9
Stop
Condition
P
Stop
Condition
P