ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 123

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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16.4 ADC REGISTERS
The ADC interfaces with the CR16A core, as shown in the
"Block Diagram" on page 1. The interface is implemented by
a set of four status and control registers, and four data reg-
isters. These registers are mapped in the address space of
the CR16A. For details on the address location of these reg-
isters, refer to Appendix A on page 156.
16.4.1 ADC Status Register (ADCST)
This is a is a byte-wide, read/write register that reports the
ADC status. Upon reset, the non-reserved bits are cleared
Bit 0 - End of Conversion (EOC)
Bit 1 - BUSY
Bit 2 - Overflow (OVF)
Bits 5-4 - Buffer Pointer (BUFPTR)
7
This bit reports the ADC conversion status. This bit is
read only and data written to it is ignored. It is written by
the hardware as follows:
0: Conversion is not complete. It is also cleared when
1: Conversion is complete. Indicates that the data was
This flag indicates that the ADC is busy converting data.
It is a read only bit and any data written to it is ignored.
It is written by the hardware as follows:
0: ADC is not busy and a new conversion can be
1: ADC is busy converting. START should not be set
0: This bit remains set until the software writes 1 to it.
1: The ADC finished conversion and attempted to
BUFPTR holds the number of the last written data reg-
ister (ADDATA0-3). BUFPTR is set to 11 when START
of the ADCCNT2 Register is changed from 0 to 1. It is a
read only field; data written to it is ignored.
Res
BUFPTR
any of the data registers is read.
placed in the buffer.
started. This bit is cleared whenever:
— ADC is disabled, (ADCEN of the ADCCNT1
— ADC is idle, (i.e., ADC is enabled, ADCEN=1,
before completion of the current conversion.
Writing 0 has no effect on this bit.
store the result in a data register (ADDATA0-3), but
it was full. A data register is full if it was written by
the ADC and was not read by the CR16A core. In
this case, the ADC overrides the data in the ADDA-
TAn Register, sets OVF and continues operation.
00
01
10
11
6
Register is cleared)
and not converting).
BUFPTR
5
Last Written Data Register
4
ADDATA0
ADDATA1
ADDATA2
ADDATA3
Res
3
Analog to Digital Converter (ADC) - January 1998
OVF BUSY EOC
2
1
0
123
16.4.2 ADC Control Register 1 (ADCCNT1)
This is a byte-wide, read/write register that enables the ADC
and the internal reference. In addition, it configures the in-
terface scheme. Changing bits 1 through 7 of ADCCNT1
while the module is active is not allowed. The ADC is active
while START of the ADCCNT2 Register or BUSY of the
ADCST Register are set. Upon reset, the non-reserved bits
of ADCCNT1 are cleared.
Bit 0 - ADC Enable (ADCEN)
Bit 1 - Internal V
Bit 2 - Interrupt Enable (INTE)
16.4.3 ADC Control Register 2 (ADCCNT2)
The ADCCNT2 Register is a byte-wide, read/write register
that configures the A/D converter into a specific mode of op-
eration. CHANNEL, CONT and SCAN should be changed
only while START=0. Upon reset, all bits of ADCCNT2 are
cleared (0).
START Res
7
0: When the software clears this bit, the ADC is dis-
1: When the software sets this bit, the ADC is en-
This read/write bit selects the source of the reference
voltage. See also Figure 16-1 and Section 16.2.2.
Note: INTREF can be changed independently of AD-
CEN. However, the internal reference block is turned on
only when the ADC is enabled (ADCEN is set to 1).
Since an external capacitor is present on the V
there is a delay of approximately 50 s until the voltage
on the pin stabilizes after INTREF is set. See Section
16.2.5 on page 120.
0: An external reference voltage should be connected
1: Enables the on-chip reference voltage source and
This bit controls interrupt generation to the CR16A core.
See also Chapter 9 on page 81.
0: When cleared, the interrupt is disabled and the in-
1: When set, the interrupt is enabled. When EOC is
7
abled and the current conversion operation is ter-
minated. The status flags EOC, BUSY and OVF in
the ADCST Register and START of the ADCCNT2
Register are cleared. However, it is recommended
to disable the ADC only when it is in Idle mode (not
converting, START and BUSY are both 0). See
Figure 16-3.
abled. Conversion can be started as described in
Section 16.2.6.
to V
eration. In this case, the internal reference voltage
source is disabled and does not drain power.
connects it to the DAC input.
terrupt signal is always low.
set by the hardware (i.e., end of conversion or buff-
er full), a level high interrupt is sent to the ICU.
6
Reserved
REF
6
5
pin, as a reference voltage for the ADC op-
REF
SCAN CONT Res
5
(INTREF)
4
4
3
INTE INTREF ADCEN
3
2
2
CHANNEL
1
1
REF
0
0
pin,