ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 103

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Bit 3 - Stall After Start (STASTR)
Bit 4 - Negative Acknowledge (NEGACK)
Bit 5 - Bus Error (BER)
Bit 6 - SDA Status (SDAST)
Bit 7 - Slave Stop (SLVSTP)
13.4.3 ACB Control Status Register (ACBCST)
The ACBCST Register is a byte-wide, read/write register
that maintains current ACB status and controls several ACB
module functions. The functions of the CBCST are de-
scribed below. Upon reset and when the module is disabled
the non-reserved bits of ACBCST are cleared (0).
This bit is set by the successful completion of an ad-
dress sending (i.e., a Start Condition sent without a bus
error, or negative acknowledge), if ACBCTL1.STAS-
TRE is set. This bit is ignored in slave mode. When
STASTR is set, it stalls the ACCESS.bus by pulling
down the SCL line, and suspends any further action on
the bus (e.g., receive of first byte in Master Receive
mode). In addition, if ACBCTL1.INTEN is set, it also
causes the ACB module to send an interrupt to the
CR16A. Writing 1 to STASTR clears it. It is also cleared
when the module is disabled and is always cleared
when STASTRE is cleared. Writing 0 to STASTR has no
effect.
This bit is set by hardware when a transmission is not
acknowledged on the ninth clock. (In this case SDAST
is not set.) Writing 1 to NEGACK clears it. It is also
cleared when the module is disabled. Writing 0 to
NEGACK is ignored.
BER is set by the hardware when a Start or Stop Condi-
tion is detected during data transfer (i.e., Start or Stop
Condition during the transfer of bits 2 through 8 and ac-
knowledge cycle), or when an arbitration problem is de-
tected. Writing 1 to BER clears it. It is also cleared when
the module is disabled. Writing 0 to BER is ignored.
When set, this bit indicates that the SDA data register is
waiting for data (transmit - master or slave) or holds data
that should be read (receive - master or slave). This bit
is cleared when reading from the ACBSDA register dur-
ing a receive, or when written to during a transmit.]
When ACBCTL1.START is set, reading ACBSDA regis-
ter does not clear SDAST. This enables the ACB to
send a repeated start in master receive mode.
If set, SLVSTP indicates that a Stop Condition was de-
tected after a slave transfer (i.e., after a slave transfer in
which MATCH or GCMATCH was set). Writing 1 to
SLVSTP clears it. It is also cleared when the module is
disabled. Writing 0 to SLVSTP is ignored.
GCMTCH
7
3
Reserved
MATCH
2
6
TGSCL
BB
5
1
ACCESS.bus (ACB) Interface
TSDA
BUSY
0
4
103
Bit 0 - BUSY
Bit 1 - Bus Busy (BB)
Bit 2 - Address Match (MATCH)
Bit 3 - Global Call Match (GCMTCH)
Bit 4 - Test SDA Line (TSDA)
Bit 5 - Toggle SCL Line (TGSCL)
When BUSY is set (1), this indicates that the ACB mod-
ule is in one of the following states:
-
-
-
-
The BUSY bit is cleared by the completion of any of the
above states, and by disabling the module. BUSY is a
read only bit. It should always be written 0.
When set (1), BB indicates the bus is busy. It is set when
the bus is active (i.e., a low level on either SDA or SCL),
or by a Start Condition. It is cleared when the module is
disabled, on detection of a Stop Condition, or when writ-
ing ‘1’ to this bit. See Section 13.5 for a description of
the use of this bit.
In slave mode, MATCH is set (1) when ACBAD-
DR.SAEN is set and the first seven bits of the address
byte (the first byte transferred after a Start Condition)
matches the 7-bit address in the ACBADDR register. It
is cleared by Start Condition, a repeated start and a
Stop Condition (including illegal Start or Stop Condi-
tion).
In slave mode, GCMTCH is set (1) when ACBCTL1.GC-
MEN is set and the address byte (the first byte trans-
ferred after a Start Condition) is 00h. It is cleared by
Start Condition, a repeated Start and a Stop Condition
(including illegal Start or Stop Condition).
Reads the current value of the SDA line. This bit can be
used while recovering from an error condition in which
the SDA line is constantly pulled low by a slave that
went out of synch. This bit is a read-only bit. Data written
to it is ignored.
This bit enables toggling the SCL line during the process
of error recovery. When the SDA line is low, writing 1 to
this bit toggles the SCL line for one cycle. Writing 1 to
TGSCL while SDA is high, is ignored. The bit is cleared
when the clock toggle is completed.
Generating a Start Condition
In Master mode (ACBST.MASTER is set)
In Slave mode (ACBCST.MATCH or ACBCST.GMATCH
is set)
In the period between detecting a Start condition
and completing the reception of the address byte.
After this, the ACB either becomes not busy or en-
ters slave mode.