ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 117

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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15.3 WATCHDOG OPERATION
The WATCHDOG is an 8-bit down counter, operating on the
rising edge of its currently selected clock source. Upon re-
set, it is disabled (i.e., it does not count and no WATCH-
DOG signal is generated). A write to the WATCHDOG
Count Register (WDCNT) or a write to the WATCHDOG
Service Data Match (WDSDM) Register starts the counter.
Once started, only reset can stop the WATCHDOG.
Writing to the WDCNT Register (when WDCFG.LWD-
CNT=0) starts the WATCHDOG counting down from the
written value. If the service on data match is enabled (WD-
CFG.WDSDME = 1), writing to the WDSDM Register with
5Ch restarts the WATCHDOG counter from the value
stored in WDCNT. Any other data causes a WATCHDOG
signal.
A WATCHDOG signal is triggered if:
WATCHDOG Clock Source Selection
Select the clock source as follows:
Changing the WATCHDOG clock source may cause it to
gain or lose one clock cycle.
Notes:
1. When TWCP.MDIV=0, the WATCHDOG counter may
2. Avoid entering Idle mode in the first four low frequency
15.4 TWD CONTROL AND CONFIGURATION
The TWD Configuration Register (TWCFG) allows you to:
Once LTWCFG, LTWCP, LTWDT0 or LWDCNT are set in
the TWCFG Register, their respective resources are locked
and may be cleared only by reset. Setting any of these reg-
isters prevents runaway software from tampering with the
respective WATCHDOG function.
15.5 OPERATION IN IDLE MODE
The TWD is active in Idle mode. In this mode, the counters
continue to function. All registers are accessible in Active
mode only.
Write operations to TWCP, TWDT0 and WDCNT may be
delayed by up to 3 32.768 KHz clock cycles. The software
should avoid entering Idle mode during this period.
The counter reaches zero (too late service)
The WATCHDOG is written to more than once per
WATCHDOG clock cycle for the currently selected
clock (too early service).
TWCFG.WDCT01 = 0
TWCFG.WDCT01 = 1
skip one count when loaded with a new value.
clock cycles after first activating the WATCHDOG.
Set the WATCHDOG clock source: T0IN or T0OUT
Enable WATCHDOG service on write to WDSDM Reg-
ister
Define which of TWCFG, TWCPR, TWDT0, T0CSR
and WDCNT is locked.
T0OUT
T0IN
Timer and WATCHDOG (TWD)
117
15.6 TWD REGISTERS
15.6.1 Timer and WATCHDOG Configuration
The TWCFG Register is a byte wide, read/write register. It
defines the WATCHDOG clock input and service method
and enables TWD control registers locking. Setting the re-
quired configuration and locking the TWCFG, stops the
software from interfering with the WATCHDOG operation.
Upon reset, the non-reserved bits of TWCFG are initialized
to 0.
7 6
Bit 0 - Lock TWCFG Register (LTWCFG)
Bit 1 - Lock TWCP Register (LTWCP)
Bit 2 - Lock TWDT0 Register (LTWDT0)
Bit 3 - Lock WDCNT Register (LWDCNT)
Bit 4 - WATCHDOG Clock from T0IN (WDCT0I)
Bit 5 - WATCHDOG Service on Data Match Enable (WDSDME)
15.6.2 Timer and Watchdog Clock Pre-Scaler Register
The TWCP Register is a byte wide, read/write register. It de-
fines the pre-scale ratio of the input clock and generates the
T0IN clock. Upon reset, the non-reserved bits of TWCP are ini-
tialized to 0.
Res WDSDME WDCT0I LWDCNT LTWDT0 LTWCP LTWCFG
7
When cleared (0), enables read/write from/to the
TWCFG Register. When set (1), any data written to it is
ignored and reading from it returns unpredictable val-
ues. Once LTWCFG is set, it can only be cleared by re-
set.
When cleared (0), enables read/write from/to the TWCP
Register. When set (1), any data written to it is ignored
and reading from it returns unpredictable values. Once
LTWCP is set, it can only be cleared by reset.
When cleared (0), enables read/write from/to the
TWDT0 and T0CSR Registers. When LTWDT0 is set
(1), the registers cannot be written to, and TWDT0 can-
not be read. Any data written to TWDT0 or T0CSR is ig-
nored. Reading from TWDT0 returns unpredictable
values. Once LTWDT0 is set, it can only be cleared by
reset.
When cleared (0), enables write to the WDCNT Regis-
ter. When set (1), any data written to it is ignored and
reading from it returns unpredictable values. Once
LWDCNT is set, it can only be cleared by reset.
When cleared (0), selects the T0OUT clock as the
WATCHDOG clock. When set (1), selects T0IN as the
input clock. The hardware clock source selection over-
rides this clock selection.
When cleared (0), disables the watchdog service using
the WDSDM Register. In this case, the WATCHDOG
should be serviced by writing a value to the WDCNT
Register. When set (1), selects the use of data match
using the WDSDM mechanism. When this bit is cleared,
write operations to WDSDM are ignored.
Registers (TWCFG)
(TWCP)
5
Reserved
4
3
4
2
2
MDIV
1
0
0