ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 45

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

3.5 BIU REGISTERS
3.5.1
The BCFG Register is a byte-wide, read/write register that
controls the configuration of common features to all zones.
On reset, BCFG is initialized to 07h.
Bit 0 - Early Write or Late Write (EWR)
Bit 1 - Observability (OBR)
3.5.2
The IOCFG Register is a word-wide, read/write register that
controls the configuration of the I/O zone. On reset, IOCFG
is initialized to 069Fh.
Bits 2-0 - WAIT
Bits 4,3 - HOLD
Bit 7 - Bus Width (BW)
7
BW
15
0: Late Write
1: Early Write
Address and Status Observability of Internal Accesses.
0: Address and status of internal accesses are not
1: Address and status of internal accesses are ob-
Number of TIW clock cycles that extend the bus cycle.
000: None
001: One
010: Two
011: Three
100: Four
101: Five
110: Six
111: Seven
Number of T
00: None
01: One
10: Two
11: Three
BW defines the external bus-width used for the I/O
zone. Bus width is initialized during reset to its default
value.
0: 8-bit bus
1: 16-bit bus (default)
7
observable. No toggle of external buses.
servable. External buses toggle.
6
BIU Configuration Register (BCFG)
I/O Zone Configuration Register (IOCFG)
Reserved
Reserved
hold
Reserved
5 4
clock cycles.
HOLD
3 2
10
2
OBR
1
IPST Res
WAIT
9
Bus Interface Unit (BIU)
EWR
0
0
8
45
Bit 9 - Post Idle (IPST)
3.5.3
The SZCFGn Register (where n = 0 or 1) is a word-wide,
read/write register that controls the configuration of zone n.
On reset, SZCFGn is initialized to 069Fh.
Bits 2-0 - WAIT
Bits 4,3 - HOLD
Bit 5 - Burst Read Enable (BRE)
Bit 6 - Wait on Burst Read WBR)
Bit 7 - Bus Width (BW)
15
BW
7
An idle cycle follows the current bus cycle, when the
next bus cycle is in a different zone
0: No idle cycle inserted
1: Idle cycle inserted
Number of TIW clock cycles that extend the bus cycle.
000: None
001: One
010: Two
011: Three
100: Four
101: Five
110: Six
111: Seven
These bits are ignored when SZCFGn.FRE bit is 1.
Number of T
00: None
01: One
10: Two
11: Three
These bits are ignored when SZCFGn.FRE bit is 1.
0: Disabled
1: Enabled
This bit is ignored when SZCFGn.FRE bit is 1.
WBR determines if a wait state is added on Burst Read
transaction.
0: No TBW on burst read cycles
1: TBW on burst read cycles
This bit is ignored when SZCFGn.FRE bit is 1 or when
SZCFGn.BRE is 0.
BW defines the width of the external bus used for the
zone. BW is initialized during reset to its default value.
0: 8-bit bus
1: 16-bit bus (default)
WBR
Static Zone Configuration Register (SZCFGn)
Reserved
6
BRE
hold
5
clock cycles.
4
12
HOLD
FRE
11
3
IPRE IPST
.
10
2
WAIT
9
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