ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 83

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Bit 1 - PFAIL Pin Value (PIN)
9.3.3
The IVCT Register is a byte-wide, read only register. It holds
the vector number of the interrupt vector. IVCT is set to 20h
upon reset.
Bits 3-0 -Interrupt Vector (INTVECT)
9.3.4
The IENAM Register is a word-wide, read/write register.
Each of the bits of IENAM enables the respective interrupt
input of the ICU (i.e., bits 0 through 15 correspond to INT0
through INT15, respectively). IENAM is cleared on reset.
IENAM bits can be cleared only when interrupts are dis-
abled. Each bit is encoded as follows:
9.3.5
The IPEND Register is a word-wide, read only register. It in-
dicates which interrupts are pending, regardless of the con-
tents of the corresponding IENAM bit. Bits 0 through 15 of
IPEND correspond to interrupts INT0 through INT15, re-
spectively. After reset, IPEND bits are undefined. Each bit
is encoded as follows:
9.3.6
The IECLR Register is a word-wide, write only register used
to clear pending, edge-triggered interrupts. Writing to the bit
positions of level-triggered interrupts has no effect. Bits 0
through 15 of IECLR correspond to INT0 through INT15, re-
spectively. Each bit is encoded as follows:
9.3.7
The IELTG Register is a word-wide, read/write register.
Each bit defines the way that the corresponding interrupt re-
quest is triggered, either edge-sensitive or level-sensitive.
Bits 0 through 15 of IETLG correspond to INT0 through
INT15, respectively. Each of IELTG bits is encoded as fol-
lows:
Holds the current (non-inverted) PFAIL pin value. PIN is
a read only bit; data written to it is ignored.
This field contains the encoded value of the highest pri-
ority, enabled, pending interrupt. It is valid during an in-
terrupt acknowledge core bus cycle in which IVCT is
read. It may contain invalid data when INTVECT is up-
dated.
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt not pending
1: Interrupt pending
0: No effect
1: Clear the corresponding pending interrupt
0: Level-sensitive
1: Edge-sensitive
7
0
Interrupt Vector Register (IVCT)
Interrupt Enable and Mask Register (IENAM)
Interrupt Pending Register (IPEND)
Edge Interrupt Clear Register (IECLR)
Edge/Level Trigger Configuration Register (IELTG)
6
0
5
1
4
0
3
INTVECT
Interrupt Control Unit (ICU)
0
83
9.3.8
The ITRPL Register is a word-wide, read/write register. It
controls the triggering polarity of the ICU. Bits 0 through 15
of ITRPL correspond to INT0 through INT15, respectively.
Each of ITRPL bits is encoded as follows:
Level-sensitive trigger type:
Edge-sensitive trigger type:
9.4 USAGE HINTS
9.4.1
1. Initialize the INTBASE register of the core.
2. Program the interrupts’ triggering mode and polarity.
3. Prepare the interrupt routines of the interrupts used.
4. Clear pending edge-interrupts used.
5. Set the relevant bits of IENAM.
6. Enable the core interrupt.
9.4.2
To prevent spurious interrupts (CR16A detection of inter-
rupts not reflected by IVCT), perform the following opera-
tions only when interrupts are disabled:
1. Clearing an interrupt request
2. Changing the triggering mode or polarity
3. Clearing IENAM bits. These bits should be cleared while
9.4.3
You can use the IENAM Register in interrupt handlers to al-
low nesting of interrupts. When the core acknowledges an
interrupt, it disables maskable interrupts by clearing the
PSR.I bit, and executes the interrupt service routine. This
routine can enable nested interrupts by setting the PSR.I
bit, and can use the IENAM Register to control which inter-
rupts are allowed.
0: Low level
1: High level
0: Falling edge
1: Rising edge
the CR16A interrupts are disabled (i.e., PSR.I bit and/or
PSR.E bit is cleared).
Trigger Polarity Configuration Register (ITRPL)
Initializing
Clearing
Nesting