ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 27

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

2.4.3
The loads connected to the strap pins should prevent the
voltage on them from dropping below V
should be high (1), or rising above V
be low (0). See Table 19-7 on page 135.
If the load caused by the system on the strap pins exceeds
10 A when V
ther an external pull-up resistor or a smaller pull-down resis-
tor to keep the pin at 1 or 0, respectively.
2.4.4
When the PC87570 is in Idle mode and shared memory with
host BIOS is enabled, the A(16-18) signals are forced to the
value sampled on the strap input that shares the pin. This is
done to reduce leakage currents on external resistors con-
nected to that pin.
Note: A(16-17) are reserved strap inputs that should not
HDEN Disables host interface;
Strap
TRIS Normal operation
Pin
be pulled to 1.
System Load on Strap Pins
Strap Inputs During Idle Mode
must be enabled using
the motherboard PnP
protocol after each reset
Internal Pull-Down (0)
CC
= 5.0V or 5 A when V
PA2/HMEMWR
PA1/HMEMRD
PA0/HMEMCS
Pin Name
PA3/HA16
PA4/HA17
PA5/A16
PA6/A17
Enables host interface
to its default settings
(legacy address of KBC,
RTC and PMC)
Causes PC87570 to
float all its output and
I/O signals for ISE use
External Pull-Up (1)
STRl
STRh
Table 2-5. Alternate Function Mapping
CC
when they should
Signal/Pin Connection and Description
= 3.3V, use ei-
when the pins
Name
PA0
PA1
PA2
PA3
PA4
PA5
PA6
Port Signal
27
Type
I/O
2.4.5
The STRPST Register is a byte-wide, read-only register. It
enables the software to read the value set to strap pins dur-
ing power-up reset. STRPST bits provide the value of their
respective strap input. See Table 2-5 for bit details.
2.5 ALTERNATE FUNCTIONS
The PC87570 uses the GPIO port pins to multiplex func-
tions and thereby maximize the device’s flexibility, as
shown in Table 2-5. You select alternate pin functions
through the configuration registers and strap options, as fol-
lows:
When a pin is used as GPIO and not in its alternate function,
disable the alternate function in the module’s register to pre-
vent wired effects.
Table 2-5 lists the I/O pins and their alternate functions.
When you use a pin as GPIO, you should disable the alter-
nate function in the module register to prevent wired effects.
7
The SHBM strap pin (see Table 2-4) controls the PA
pins. When SHBM = 1, the pins function as GPIO port
signals. When SHBM=0, they function as described in
Section 5.2.1 on page 49.
The ports’ Alternate Function Control Register controls
the PB, PC, PD and PE pins. Each of the ports’ pins
may be used as a GPIO port or in its alternate function.
The environment setting and MCFG bits control port
PF and PG pins.
The environment setting controls port PH pins. When
in Dev environment, the pins perform their alternate
functions. In IRE or IRD environments, they function
as GPIO ports.
Reserved
HMEMWR
Strap Pin Status Register (STRPST)
HMEMCS
HMEMRD
Alternate
Function
HA16
HA17
A16
A17
(Alternate Function)
3
SHBM=0
HDEN
Select
2
HRMS
1
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SHBM
0