ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 70

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

Bit 7 - Update in Progress (UIP)
6.3.2
Bit 0 - Daylight Saving Enable (DSE)
Bit 1 - 24 or 12 Hour Mode (HM)
Bit 2 - Data Mode (DM)
This is a read/write bit which is reset at power-up reset only.
Bit 3 - Unused
Table 6-4. Divider Chain Control and Bank Selection
SET
CRA
DV2
7
This is a read only bit which is reset at power-up reset
only.
This bit reads 0 when bit 7 of the CRB Register is 1.
1: Timing registers updated within 244 s
0: Timing registers not updated within 244 s
This is a read/write bit which is reset at power-up reset
only.
1: Daylight saving feature enabled, as follows:
0: Daylight saving feature disabled
This is a read/write bit which is reset at power-up reset
only.
1: 24 hour format enabled
0: 12 hour format enabled
1: Binary format enabled
0: BCD format enabled
This bit is defined as “Square Wave Enable” by the
MC146818 and is not supported by the RTC. This bit is
always read as 0.
6
0
0
0
0
1
1
1
1
In the spring, time advances from 1:59:59 AM to
3:00:00 AM on the first Sunday in April.
In the fall, time returns from 1:59:59 AM to
1:00:00 AM on the last Sunday in October.
RTC Control Register B (CRB)
PIE
CRA
6
DV1
5
0
0
1
1
0
0
1
1
AIE
5
CRA
DV0
4
0
1
0
1
0
1
0
1
UIE
Undefined
4
Selected
Bank 0
Bank 0
Bank 0
Bank 1
Bank 2
Bank 0
Bank 0
Bank
Real-Time Clock (RTC) and Advanced Power Control (APC)
3
0
Divider Chain Reset
Divider Chain Reset
Oscillator Disabled
Oscillator Disabled
Normal Operation
Normal Operation
Normal Operation
DM
Configuration
2
Test
HM
1
DSE
0
70
Bit 4 - Update Ended Interrupt Enable (UIE)
Bit 5 - Alarm Interrupt Enable (AIE)
Bit 6 - Periodic Interrupt Enable (PIE)
Bit 7 - Set Mode (SET)
6.3.3
Bits 3-0 - Reserved
Bit 4 - Update Ended Interrupt Flag (UF)
Bit 5 - Alarm Interrupt Flag (AF)
Bit 6 - Periodic Interrupt Flag (PF)
IRQF
7
This is a read/write bit that is reset to 0 on RTC reset.
1: Generation of Update Ended interrupt enabled.
0: Generation of Update Ended interrupt disabled
This is a read/write bit that it is reset to 0 on RTC reset
(i.e., any reset and when SIBCST1.RTCMR is set).
1: Generation of Alarm interrupt enabled. This inter-
0: Generation of alarm interrupt disabled
This is a read/write bit that is reset to 0 on RTC reset
(i.e., any reset and when SIBCST1.RTCMR is set)
1: Generation of Periodic interrupt enabled. Bits 3-0 of
0: Generation of Periodic interrupt disabled
This is a read/write bit that is reset at power-up reset
only. See also Section 6.2.10 on page 66.
1: The user copy of time is “frozen”, allowing the time
These bits always return 0.
This is a read/write bit that is reset to 0 on RTC reset
(i.e., any reset and when SIBCST1.RTCMR is set). In
addition, this bit is reset to 0 when this register is read.
1: Time registers updated
0: No update occurred since the last read
This is a read/write bit that is reset to 0 on RTC reset
(i.e., any reset and when SIBCST1.RTCMR is set). In
addition, this bit is reset to 0 when this register is read.
1: Alarm condition detected
0: No alarm detected since the last read
This is a read/write bit that is reset to 0 on RTC reset
(i.e., any reset and when SIBCST1.RTCMR is set). In
addition, this bit is reset to 0 when this register is read.
1: Transition occurred on the selected tap of the divid-
0: No transition occurred on the selected tap since the
0: Timing updates occur normally.
This interrupt is generated when an update occurs.
rupt is generated immediately after a time update in
which the seconds, minutes, and hours time equal
their respective alarm counterparts.
the CRA Register determine its rate.
registers to be accessed whether or not an update
occurs.
er chain
last read
RTC Control Register C (CRC)
PF
6
AF
5
UF
4
3
2
Reserved
1
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0