ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 102

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

If an address match, or a global match, is detected:
Slave Receive and Transmit
Slave Receive and Transmit are performed after a match is
detected and the data transfer direction is identified. After a
byte transfer the ACB module extends the acknowledge
clock until the software reads or writes the ACBSDA regis-
ter. The receive and transmit sequences are identical to
those used in the master routine.
Slave Bus Stall
When operating as a slave, the PC87570 stalls the AC-
CESS.bus by extending the first clock cycle of a transaction
in the following cases:
Slave Error Detection
The ACB detects illegal Start and Stop Conditions on the
ACCESS.bus (i.e., a Start or Stop Condition within the data
transfer or the acknowledge cycle). When an illegal Start or
Stop Condition is detected, the BER bit is set and MATCH
and GMATCH are cleared, setting the module to be an un-
addressed slave.
13.3.3 Power-Down
When the PC87570 is in Idle mode, the ACB module is not
active but retains its status. If the ACB is enabled
(ACBCTL2.ENABLE=1), on detection of a Start Condition,
a wake-up signal is issued to the MIWU. This signal may be
used to switch the PC87570 to Active mode.
The ACB module can not check the address byte, following
the start condition that woke up the PC87570, for a match.
The ACB responds with a negative acknowledge, and the
device should re-send both the Start Condition and the ad-
dress after the PC87570 has had time to wake up.
Check that the ACBCST.BUSY bit is inactive before enter-
ing Power Save or Idle mode. This guarantees that the
PC87570 does not acknowledge an address sent, and
stops responding later.
13.3.4 SDA and SCL Pin Configuration
The SDA and SCL are open collector signals. The PC87570
permits the user to define whether to enable or disable
these signals. SDA and SCl are enabled with internal weak
pull-up, as shown in Table 19-7 on page 135. For more in-
formation about configuring these pins, see Table 2-5 on
page 27.
The PC87570 asserts its SDA pin during the acknowl-
edge cycle
The ACBCST.MATCH and ACBST.NMATCH bits are
set. If ACBST.XMIT=1 (i.e., Slave Transmit mode)
ACBST.SDAST is set to indicate that the buffer is
empty.
If ACBCTL1.INTEN is set, an interrupt is generated if
both the ACBCTL1.INTEN and ACBCTL1.NMINTE
bits are set.
The software then reads the ACBST.XMIT bit to iden-
tify the direction requested by the master device. It
clears the ACBST.NMATCH bit so future byte transfers
are identified as data bytes.
ACBST.SDAST is set.
ACBST.NMATCH, and ACBCTL1.NMINTE are set.
ACCESS.bus (ACB) Interface
102
13.3.5 ACB Clock Frequency Configuration
The ACB module permits the user to set the clock frequency
used for the ACCESS.bus clock. The clock is set by the
ACBCTL2.SCLFRQ field. This field determines the SCL
clock period used by the PC87570. This clock low period
may be extended by stall periods initiated by the ACB mod-
ule or by another ACCESS.bus device. In case of a conflict
with another bus master, a shorter clock high period may be
forced by the other bus master until the conflict is resolved.
13.4 ACB REGISTERS
13.4.1 ACB Serial Data Register (ACBSDA)
The ACBSDA Register is a byte-wide, read/write shift regis-
ter used to transmit and receive data. The most significant
bit is transmitted (received) first and the least significant bit
is transmitted (received) last. Reading or writing to the ACB-
SDA register is allowed only when ACBST.SDAST is set, or
when for repeated starts after setting the START bit. An at-
tempt to access the register in other cases may produce un-
predictable results.
13.4.2 ACB Status Register (ACBST)
The ACBST Register is a byte-wide, read-only register.
Some of its bits may be cleared by software, as described
below. This register maintains current ACB status. Upon re-
set, and when the module is disabled, ACBST is cleared
(00h).
Bit 0 - Transmit Mode (XMIT)
Bit 1 - Master Mode (MASTER)
BIt 2 - New Match (NMATCH)
7
This bit is set when the ACB module is currently in mas-
ter/slave transmit mode. Otherwise it is cleared.
When set, this bit indicates that the module is currently
in Master mode. It is set when a request for bus master-
ship succeeds. It is cleared on arbitration loss (BER is
set) or the recognition of a Stop Condition.
This bit is set when the address byte following a Start
Condition, or repeated start, causes a match or a global-
call match. NMATCH is cleared when writing 1 to it.
Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is
set, an interrupt is sent when this bit is set.
STASTR
SLVSTP
7
3
NMATCH
SDAST
6
2
DATA
MASTER
BER
5
1
NEGACK
XMIT
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