ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 124

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

Bits 2-0 - Analog Input Channel Select (CHANNEL)
Bit 3- Reserved
Bit 4 - Continuous Conversion (CONT)
Bits 5 - SCAN
Bit 6 - Reserved
Bit 7 - START
These bits control the input multiplexer and select the
channel to be connected to the Sample and Hold block
(see Figure 16-1). When using a scan mode, it specifies
the first channel to be converted. The software should
configure this field before setting START.
This bit is 0 after reset. Always write zero to this bit.
When set, a new conversion starts after completion of
the current conversion cycle (or conversion burst). The
software should configure this field before setting
START.
0: Single conversion, or one burst of four conversions
1: Continuous conversion
This bit defines whether a single channel or a burst of
four channels is scanned. The software should config-
ure this field before setting START.
0: One channel
1: Four channel scan
This bit is 0 after reset. Always write zero to this bit.
This bit can be set by the software to initiate a conver-
sion cycle. The conversion mode is defined by bits 4 and
5 of this register. The software should not set this bit
while BUSY of the ADCST Register is set.
0: When cleared, the current conversion process is
1: When set by the software, the conversion process
Table 16-4. Analog Input Channel Selection
completed and no subsequent conversion begins
until this bit is set again.
— In single conversion modes (one or four chan-
— In continuous conversion modes, the hardware
begins.
CHANNEL Bits
nels, see bits 4 and 5 of this register), START is
automatically cleared by the hardware upon
completion of the conversion(s).
does not clear this bit.
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Selected Channel
Analog to Digital Converter (ADC) - January 1998
0
1
2
3
4
5
6
7
124
16.4.4 ADC Control Register 3 (ADCCNT3)
The ADCCNT3 Register is a byte-wide, read/write register.
ADCCNT3 should be written only when the ADC is disabled
(ADCEN of the ADCCNT1 Register is 0). Upon reset, non-
reserved bits of ADCCNT3 are cleared (0).
Bits 2-0 - ADC Clock Divide (CDIV)
Bits 5-3 - DELAY
Reserved
7
CDIV defines the ratio between the system clock fre-
quency and the ADC clock frequency. The CDIV should
be programmed to guarantee that the ADC conversion
clock is up to 1 MHz. See Figure 16-1 and Chapter 7 on
page 76.
This field allows the user to adjust the sampling time ac-
cording to the external circuits connected to the analog
inputs and the ADC clock frequency.
It defines the delay from setting START or the comple-
tion of previous conversion (in continuous or burst
modes), to the beginning of a new conversion.
The sampling time is defined in terms of ADC clock cy-
cles. It should be used to guarantee the settling time of
the internal sampling circuit. See Section 16.5.5 for fur-
ther details.
DELAY Bits
0
0
0
0
1
1
0
0
0
0
1
1
1
1
2
5
CDIV Bits
Other
1
0
0
1
1
0
0
4
0
0
1
1
0
0
1
1
6
0
0
1
0
1
0
1
3
0
1
0
1
0
1
0
1
Table 16-6. Sampling Time
Table 16-5. CDIV Ratios
5
System Clock to Conversion Clock
DELAY
(Conversion Clock Cycles)
4
Frequency Ratio
Sampling Time
3
Reserved
Reserved
16
32
16
32
64
1
2
4
8
1
2
4
8
2
CDIV
1
www.national.com
0