ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 53

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

5.10.1 IRQ1, IRQ12 and IRQ11 and IRQ8 Buffers
The PC87570 drives the IRQ pins (IRQ1, IRQ12 and
IRQ11) using either open drain or push-pull buffers. The
buffer type is configured by PSPE in the HIIRQC Register.
When used as open drain, an external pull-up resistor is re-
quired to pull the signal high.
5.11 SYSTEM CONSIDERATIONS
5.11.1 Reset Configuration
During reset, the host configuration channel is initialized to
its default state, as follows:
5.11.2 Host Power-On (HPWRON) Indication Input
The PC87570 can operate when the host power is discon-
nected. In this case, the signals from the host may present
undefined states to the PC87570. A special input pin, HP-
WRON, enables the PC87570 to check the host power sup-
ply state and prevent errors caused when the supply is not
active.
When HPWRON is low, all the host interface inputs are ig-
nored and all outputs are either TRI-STATE or forced low,
according to their reset values. See “Basic Configuration”
on page 3.
When HPWRON is high, the PC87570 responds to host bus
cycles and outputs signals to it.
The modules’ address registers are initialized to the
device legacy address.
The Function Enable Register is initialized according
to the HDEN strap input.
Access to the chip base address configuration Index
and Data Registers is disabled.
A motherboard PnP escape sequence is enabled.
Configuration lock bits are cleared.
HIIRQC.IRQxB
HIIRQC.IRQxB
(read)
(write)
HIIRQ.IRQM
Hardware
Interrupt
HIIRQC.IRQxB
Figure 5-4. IRQ1, IRQ12 or IRQ11 Control
HIIRQC.IRQNPOL
1
0
Host Bus Interface (HBI)
HICTRL.PMHIE or
HICTRL.OBFMIE or
HICTRL.OBFKIE
53
When the IRQE Register is set to disable IRQ1, IRQ12,
IRQ11, or IRQ8, its respective pin is put into TRI-STATE,
overriding any other settings in the host interface.
Figure 5-4 illustrates the effect of the different control bits on
the IRQ signals.
5.11.3 Host Master Reset (HMR) Input
The PC87570 is reset by an internal reset signal generated
on the rising edge of its power supply. The chip is also reset
on the rising edge of the HMR pin. See more details in Sec-
tion 2.3.4.
5.11.4 Host Reset Output (HRSTO) from PC87570
HRSTO is one of the sources for host soft reset commands
(i.e., INIT input in the x86 processors). See Figure 5-5. The
host is reset when the HRSTO output is low. A reset com-
mand is issued by the PC87570 when:
.
1
0
Hardware: Strap input HRMS=1, shared memory is
enabled (SHBM=0) and accessed while the PC87570
cannot complete the memory access. In this case, the
reset lasts until the PC87570 completes shared mem-
ory access, and HMEMRD and HMEMWR are inac-
tive. After power-up reset, the HRSTO is inactive
(high). HRSTO is automatically active (low) while HP-
WRON is low.
Software: The CR16A firmware can issue a reset com-
mand to the host by writing 1 to HRSTO in the CST2
Register. The reset to the host ends by writing 0 to
this bit.
HIIRQC.PSPE
IRQE.IRQxE
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IRQx
Pin