ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 105

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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13.5 USAGE HINTS
1. When the ACB is disabled, the ACBCST.BB bit is
2. When waking up from power-down before checking
3. The BB bit is intended to solve a deadlock in which two
4. In some cases, the bus may get stuck with the SCL
Where t
mode (see Clock Output Signals in Table 19-9 on page
138).
SCLFRQ may be programmed to values in the range of
0001000
other value has unpredictable results.
cleared. After enabling the ACB (ACBCTL2.ENABLE is
set to 1) in systems with more than one master, the bus
may be in the middle of a transaction with another de-
vice, which is not reflected by BB.
To prevent bus errors, the ACB must synchronize with
the bus activity status before issuing a request to be-
come the bus master for the first time. The software
should check that there is no activity on the bus by
checking the BB bit after the bus allowed time-out peri-
od.
ACBCST.MATCH, use ACBCST.BUSY to make sure
that the address transaction is completed.
or more devices detect a usage conflict on the bus and
both cease being bus masters at the same time.
In this situation, the BB bits of both devices are active
(because each “detects” another master currently per-
forming a transaction, while in fact there is none), poten-
tially causing the bus to stay locked until some device
sends a ACBCTL1.STOP condition.
The ACBCST.BB bit allows the software to monitor bus
usage so that it can detect whether the bus remains un-
used over a certain period of time, while the BB bit is set.
It also avoids sending a STOP signal in the middle of the
transaction of some other device on the bus.
and/or SDA lines active, such as when an erroneous
Start or Stop Condition occurs in the middle of a slave
receive session. If the SCL line is stuck active, the mod-
ule that holds the bus must release it.
If the SDA line is stuck active, you can use the sequence
below to release the bus.
Note: In normal cases, SCL may be toggled only by the
bus master. This sequence is a recovery scheme which
is an exception. Use it only if there is no other master on
the bus.
a. Disable and re-enable the module to set it for the
b. Set the ACBCTL1.START bit to attempt to issue a
c. Check if the SDA line is active (low) by reading
d. Check if ACBST.MASTER is set, which indicates
a. Clear the BB bit. This enables the START bit to be
slave mode not addressed.
Start Condition.
ACBCST.TSDA bit. If yes, issue a single SCL cycle
by writing 1 to ACBCST.TGSCL bit. If the SDA line
is not active, skip to step e.
that the Start Condition was sent. If not, repeat step
c and d until the SDA is released.
executed. Continue according to “Bus Idle Error Re-
covery” on page 101.
CLK
2
(8
is the PC87570 clock cycle when in Active
10
) through 1111111
2
(127
10
ACCESS.bus (ACB) Interface
). Using any
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