ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 14

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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1.0 Introduction
1.1 INTERNAL ARCHITECTURE
The following descriptions are based on the block diagram
in Highlights on page 1.
1.1.1
The CompactRISC CR16A core is an advanced, general-
purpose, 16-bit microprocessor core with a RISC architec-
ture. The core is responsible for arithmetic and logic opera-
tions and program control. For more details about the core
structure and instruction set, see CR16A Core Architecture
Specification, Revision 1.1, January 1996.
1.1.2
The BIU controls access to:
Each of these memories is associated with a ZONE in the
BIU. The zone configuration registers control access to de-
vices connected to it. See Section 3.2 on page 34 for more
details on BIU.
1.1.3
ROM The on-chip ROM holds the CR16A boot program which
is run by the PC87570 upon reset (internal power-up reset, or
pulse on HMR pin). The 2048 byte on-chip ROM is used for
boot and External Memory update programs.
The boot program verifies that the External Memory exists
and holds a valid code; then, it jumps to execute this code.
If the External Memory does not hold a valid code (for ex-
ample, the Flash is wrongly programmed), the boot pro-
gram enables the host to download the code via the host
interface channel, and re-program the Flash.
The External Memory holds most of the PC87570 application
programs and constant data. The external memory can be any
kind of memory device since the PC87570 can directly inter-
face with Flash, ROM or SRAM devices. This allows upgrad-
ing of the PC87570 firmware (keyboard controller code) in the
field.
RAM The 1024 byte on-chip RAM is mostly used for the
storage of program variables and stack. It can store short
programs used upon returning from Idle mode to Active
mode, and is preserved as long as VCC power is applied to
the PC87570. The PC87570 hardware arbitrates Flash us-
age by the CR16A firmware and the host processor BIOS
program, when the "shared-memory" configuration is used.
To reduce resource contention when this shared BIOS
Flash scheme is used, the host processor should copy the
Flash contents to the host’s main memory (DRAM) upon
system boot. Flash sharing is based on “cycle stealing” so
both the host processor and the CR16A can execute in par-
allel code from the same memory device.
on-chip Base Memory (boot-code, ZONE1, mask-
ROM)
off-chip devices:
— Base Memory (boot-code, ZONE1, Flash or ROM)
— External Memory (application code, ZONE0, Flash
— I/O Expansion
or SRAM)
Processing Unit
BIU
Memory
Introduction
14
1.1.4
The Host Bus Interface (HBI) bridges and arbitrates be-
tween host and CR16A accesses to shared resources. The
HBI allows the host and CR16A to share Flash memory.
See Section 5.2 on page 49 for more details on the shared
memory system.
The HBI enables host access to the KBD/MOUSE and the PM
interface ports, and to the RTC/APC. It also enables the
CR16A to access the RTC/APC and its CMOS RAM.
The host interface uses an ISA compatible bus protocol.
The PC87570 decodes the 16 ISA address lines to identify
the on-chip I/O device address as defined in the host con-
figuration. Shared BIOS memory accesses to the device
are indicated by a memory chip select input from the host
(HMEMCS signal), and three additional address lines (A16,
A17 and A18).
The Host Interface Configuration
cessor to configure the interface to the PC87570 I/O devic-
es (KBD, PM and RTC/APC host interface channels). The
Host Interface Configuration includes a motherboard Plug-
and-Play protocol that allows settings, such as the address
of each device, to be enabled and disabled. It also includes
a locking scheme to allow the BIOS program to protect the
configuration from tampering.
The Host Interface has three channels as follows:
The Host Interface supports the four legacy (ISA) inter-
rupts.The PC87570 can generate interrupt requests to the
host processor via IRQ1, IRQ12, IRQ11 and IRQ8 for the
Keyboard, Mouse, PM and RTC/APC handlers, respective-
ly. This allows the PC87570 to be used with polling or inter-
rupt driven schemes.
The PC87570 communicates with a host processor over an
ISA compatible, host interface bus. The KBD, PM and the
RTC/APC are interfaced as I/O devices over the I/O ad-
dress space of the host.
In addition, the PC87570 generates the gate A20 control
signal (GA20 pin) and a soft reset signal (HRSTO pin) to the
host. Optionally, this HRSTO reset signal can be used to
prevent the host from accessing the shared Flash when the
PC87570 cannot perform the shared memory access dur-
ing the PC87570’s boot-up time.
1.1.5
The RTC/APC has a low-power clock that provides time-of-
day, a calendar with century counter and alarm features. It
can work from either V
ternal switch. Other features include three maskable inter-
rupt sources and 242 bytes of general-purpose RAM. An
external battery source maintains valid RAM and time dur-
ing V
DS1287 and MC146818.
The APC hardware, with APM 1.2 compatible power con-
trol, features such as alarm wake-up, ring detection and
host control off commands. The APC controls the PC power
supply via the CR16A firmware. This allows maximum flex-
ibility in designing an ACPI system based on the PC87570.
Keyboard and Mouse (host addresses 60h, 64h).
Power Management (host address 62h, 66h)
RTC/APC (host address 70h, 71h).
CC
HBI
Peripherals
failure. The RTC is software compatible with the
CC
or a backup battery using an in-
allows the host pro-