ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 44

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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3.3.8
Figure 3-14 shows an example of how two ports can be im-
plemented off-chip, using I/O expansion. This example im-
3.4 DEVELOPMENT SUPPORT
The BIU provides the following support for development
systems.
3.4.1
The Bus Status BST0-2 signals indicate whether a transac-
tion on the core bus was issued, and the transaction type.
See Table 18-1 on page 130.
3.4.2
The core bus monitoring cycle is a non-data transfer bus cy-
cle. It takes a single clock cycle - T1. On this cycle:
See Figure 3-15. The core bus monitoring cycle is generat-
ed only when the BCFG.OBR configuration bit is 1.
•
•
•
•
1. This routing is for late write. If early write, SELIO is routed to CP and WR0 to CE. All other routing is unchanged.
The address pins display the address of the internal de-
vice accessed on the core bus.
CBRD indicates the direction of the access (read or
write).
BE0-1 indicate which data bus bytes are accessed (low-
er or upper).
BST0-2 display the core bus status.
I/O Expansion Example
Bus Status Signals
Core Bus Monitoring
Figure 3-14. Example of an Implementation of Two Ports Using I/O Expansion
PC87570
SELIO
WR0
D0-7
RD
1
1
Bus Interface Unit (BIU)
44
8
plements two 8-bit ports, by connecting the SELIO, RD and
WR0 pins to the latch/buffer controls.
74x541
CE
CP 8-Bit
D-FF
OE1
OE2
74x377
Figure 3-15. Core Bus Monitoring Bus Cycle
Buffer
8-Bit
CLK
A0-12,
A16-18
SEL0-1
SELIO
BE0-1
WR0-1
D0-15
CBRD
RD
BST0-2
8
8
T1