ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 30

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Bit 3 - Address A15 Enable (A15E)
Bit 4 - Expansion I/O Enable (EXIOE)
BIt 5 - Clock Output Enable (CLKOE)
Bit 6 - Test Hook Set Flag (TEST)
2.6.2
The PAGE Register is a read/write, byte wide register.
When shared memory is used, this register defines the most
significant bits of the address used when the CR16A core
access the External Memory (zone 0). This defines which
part of the shared memory the PC87570 firmware uses.
During host processor access to the shared memory, the
address lines are taken from the host address bus and not
from the Page Register.
See “External Memory Mapping into Shared BIOS Memory”
on page 32 for an explanation of how the bits below are
used to map the External Memory.
2.7 SHARED MEMORY CONFIGURATION
The PC87570 can share the use of the same memory de-
vice with the host processor. Either Flash EPROM or ROM
devices may be used. The memory can be up to 512 KByte.
The PC87570 is mapped into a block of 56 KByte in the
memory device. It may use all the block or part of it.
The host can access any of the bytes in the Flash device.
The BIOS program may be stored at any location not used
by the PC87570 firmware, even within the block assigned to
it.
To share the BIOS memory, hold the SHBM strap input low
during power-up reset. The firmware should perform the fol-
lowing initialization steps after reset:
1. Set MCFG.A15E to 1 and MCFG.EXM16 according to
2. Set MCFG.SHOFF to enable access to the External
When cleared (0), the PG1/A15 pin is used as a PG1
GPIO port. When it is set (1), the pin is used to output
address line A15. This allows interface to up to 56 Kbyte
of External Memory. It is set when shared BIOS memory
mode is detected.
When cleared (0), the PG0/SELIO pin is used as a
GPIO port signal (PG0). When set (1), the pin is used to
output SELIO signal. SELIO allows the use of the I/O
Expansion protocol to implement I/O ports off-chip, in
addition to the I/O ports implemented on-chip.
When cleared (0), the PG2/CLK pin is used as a gener-
al-purpose port signal (PG2). When set (1), the port out-
puts the clock signal.
This bit is set only when the test hook is enabled. The
Base Memory should jump to the test hook routine when
this bit is identified as high. Any device used in the IRE
environment must hold this code. This is a read only bit.
When modifying the MCFG Register, always write 0 to
this bit.
the value of PH[3].
Memory.
7
Reserved
PAGE Register
3
PAGE18
2
PAGE17
1
Signal/Pin Connection and Description
PAGE16
0
30
3. Load the Page Register with the firmware’s base ad-
4. Configure the memory (zone0) access parameters (i.e.,
5. If the memory device is 512 KByte (i.e., above 256
6. Set MCFG.SHMEN only after the above configurations
Figure 2-1 describes the hardware scheme used when a
512K Byte, 8-bit wide, Flash memory is connected to the
PC87570 in the shared BIOS memory configuration.
See Section 5.2 on page 49 for more details about the
shared memory interface and the bus protocols in use.
2.8 MEMORY MAP
The memory and I/O devices are directly mapped into the
256-Kbyte address space of the CR16A. The CR16A allows
the first 128 Kbytes (00000h-1FFFFh) of its address space
to include both code and data.
The boot section code and constant data of a PC87570-
based system is stored in the Base Memory. This memory is:
Most of the code and constant data of the PC87570 is
stored in the External Memory. This memory can be either
a ROM, Flash or RAM device interfaced directly with the
PC87570. A power-up configuration pin allows memory
sharing with the host processor.
Only byte-wide transactions may access byte-wide regis-
ters, and only word-wide transactions may access word-
wide registers. Attempts to read a write-only register or write
to a read-only register cause unpredictable results.
Zeros must be written to reserved bits. Reading reserved
bits returns an undefined value. When modifying a register
with reserved bits, the data read from reserved bits can be
written back to it.
Table 2-6 shows how the PC87570’s memory and I/O de-
vices are mapped in the CR16A address space. Appendix
A on page 156 shows the address map of the registers for
the other modules.
Addresses not included in Table 2-6 or in Chapter A on
page 156 are reserved. Attempts to access unlisted ad-
dresses produce unpredictable result
dress of the Shared BIOS block that needs to be ac-
cessed.
bus width, write cycle type, number of wait and hold cy-
cles) using the Page and SZCFG0 Registers. The mem-
ory device may be either 8 or 16 bits wide; the host
interface is 8-bits wide and the PC87570 takes care of
the bus width translation.
KByte), set the PEALT.0 and PEALT.1 bits, configuring
PE0 and PE1 to be used in their alternate functions.
HA18 is used as a BIOS page select.
The External Memory may be read or written by the core,
as necessary, during steps 3 through 5, but the shared
memory cannot be accessed by the host processor.
are completed.
On-chip ROM in IRE environment
Off-chip memories (ROM, Flash or SRAM memory) in
IRD or Dev environment.
s.