ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 61

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

5.14 HBI REGISTERS ACCESSED BY HOST
The PC87570 has 14 host-accessed registers that control
the host interface channel, listed with their indexes in Table
5-4.
5.14.1 Identification Register (SID)
The SID Register identifies the chip. Its value is fixed as
00h. This register is a read only register. Data written to it is
ignored.
5.14.2 Identification Type Register (SIDT)
The SIDT Register identifies the chip type. Its value is fixed
as 01h for the PC87570. This register is a read only register.
Data written to it is ignored.
SID
SIDT
SIDR
SBAH
SBAL
RTCCSAH RTC Chip Select Address, High
RTCCSAL RTC Chip Select Address, Low
KBCCSAH KBC Chip Select Address, High
KBCCSAL KBC Chip Select Address, Low
PMCSAH
PMCSAL
FER
FLR
IRQE
MSB
MSB
Mnemonic
7
7
Table 5-4. HBI Registers Accessed by Host
6
6
Chip Identity Register
Chip Type Register
Chip Revision Register
Chip Base Address, High Register
Chip Base Address, Low Register
(HRTCCS) Register
Register
(KKBCCS) Register
Register
PM Chip Select Address, High
(HPMCS) Register
PM Chip Select Address, Low
Register
Function Enable Register
Function Lock Register
IRQ Enable Register
5
5
Register Name
ID Value
ID Value
4
4
3
3
2
2
1
1
Host Bus Interface (HBI)
Index
4Bh
4Ah
22h
26h
27h
50h
51h
52h
53h
54h
55h
56h
57h
58h
LSB
LSB
0
0
61
5.14.3 Identification Revision Register (SIDR)
The SIDR Register identifies the chip revision. Its value is
fixed as 00h for the first revision. This register is a read only
register. Data written to it is ignored.
5.14.4 Base Address High Register (SBAH)
The SBAH Register holds the high address bits of the con-
figuration Index and Data Registers’ base address.
The value of this register after reset is undefined. It is initial-
ized by the motherboard PnP protocol, described in Section
5.13.
After this register has been initialized, the address may be
updated if SBALK in the FLR Register is 0. This change is
performed using the scheme described in “Changing the
Configuration Base Address” on page 60.
Bits 0 through 7 of this register hold the host bus address bits
8 through 15, respectively.
5.14.5 Base Address Low Register (SBAL)
The SBAL Register holds the low address byte of the con-
figuration Index and Data Registers’ base address.
The value of this register after reset is undefined. It is initial-
ized by the mother board PnP protocol, described in Section
5.13.
After this register has been initialized, the address may be
updated if SBALK in the FLR Register is 0. This change is
performed using the scheme described in “Changing the
Configuration Base Address” on page 60.
Bits 0 through 7 of this register hold the host bus address
bits 0 through 7, respectively. Bit 0 is a read only bit and
holds the value 0. Data written to this bit is ignored.
5.14.6
The RTCCSAH Register holds the high address bits of the
RTC module. Bits 0 through 7 of this register hold the host
bus address bits 8 through 15, respectively. On reset, this
register is initialized to 00h. It may be updated if RTCLK in
the FLR Register is 0.
5.14.7
The RTCCSAL Register holds the low address bits of the
RTC module. Bits 0 through 7 of this register hold the host
bus address bits 0 through 7, respectively. Bit 0 is a read
only bit and hold the value 0. This bit is ignored when de-
MSB
7
7
7
7
RTC Chip Select Address High Register (RTCCSAH)
RTC Chip Select Address Low Register (RTCCSAL)
6
6
6
6
5
5
5
5
Address High HA15-8
Address High HA15-8
Address Low HA7-0
ID Value
4
4
4
4
3
3
3
3
2
2
2
2
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1
1
1
1
LSB
0
0
0
0