ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 56

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Res PMICIE PMECIE PMHIE IBFCIE OBECIE OBFMIE OBFKIE
when LKRTCHA in the CST1 Register is set. This register
actually access the Index Register located at host default
address 0070h.
5.12.4 RTC Core Data Register (RTCCD)
The RTCCD Register is a byte-wide, read/write register. A
write to this register writes the RTC Data Register. A read
from this bit reads the RTC Data Register. This register
should be accessed by the PC87570 firmware, only when
LKRTCHA in the CST1 Register is set. This register actually
access the Data Register located at host default address
0071h.
5.12.5 Host PnP Initial Configuration Base Address
Both HCFGBAL and HCFGBAH are byte-wide, read/write reg-
isters. HCFGBAL holds the least significant byte of a host
motherboard PnP initial configuration address, and HCFG-
BAH holds the most significant byte. The contents of HCFG-
BAH and HCFGBAL do not change during a warm reset
(HMR).
Data written to this register pair can be used to select the
PC87570 during the host motherboard PnP configuration
sequence. Data is considered valid (and is used for address
compare) only when VHCFGA in the CST2 Register is set.
To update the host initial PnP configuration address pro-
ceed as follows:
1. Clear VHCFGA in the CST2 Register.
2. Write the lower byte of the address to HCFGBAL.
3. Write the higher byte of the address to HCFGBAH.
4. After the write to HCFGBAH is completed, the hardware
On power-up and WATCHDOG reset, this register is unde-
fined. When HCFGLK in the CST2 Register is set, it locks the
current setting of HCFGBAL and HCFGBAH.
5.12.6 Host Interface Control Register (HICTRL)
The HICTRL Register is a byte wide, read/write register,
used in setting host interface mechanism options. On reset,
non-reserved bits of HICTRL are cleared.
7
MSB
MSB
A15
A7
7
7
7
7
automatically sets the VHCFGA bit in the CST2 Regis-
ter.
6
Low and High Registers (HCFGBAL/H)
6
6
6
6
5
Host PnP Address High
Host PnP Address Low
5
5
5
5
RTC Address
4
RTC Data
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
Host Bus Interface (HBI)
LSB
LSB
A0
A8
0
0
0
0
0
56
Bit 0 -Output Buffer Full Keyboard Interrupt Enable (OBFKIE)
Bit 1 - Output Buffer Full Mouse Interrupt Enable (OBFMIE)
Bit 2 - Output Buffer Empty Core Interrupt Enable (OBECIE)
Bit 3 - Input Buffer Full Core Interrupt Enable (IBFCIE)
Bit 4 - PM Host Interrupt Enable (PMHIE)
Bit 5 - PM Output Buffer Empty Core Interrupt Enable (PMECIE)
Bit 6 - PM Input Buffer Full Core Interrupt Enable (PMICIE)
5.12.7 Host Interface IRQ Control Register (HIIRQC)
The HIIRQC Register is a byte wide, read/write register. It
controls the IRQ signals mode of operation. On reset, HI-
IRQC is preset to 07h.
PSPE IRQNPOL
7
0: IRQ1 interrupt signal is controlled by IRQ1B bit in
1: Enables Output Buffer Full interrupt to the keyboard
0: IRQ12 interrupt signal is controlled by IRQ12B bit in
1: Enables Output Buffer Full interrupt to the mouse
0: Interrupt signal low
1: Enables Output Buffer Empty interrupt to the
0: Interrupt signal low
1: Enables Input Buffer Full interrupt to the CR16A
0: IRQ11 interrupt signal is controlled by IRQ11B bit in
the HIIRQC Register
1: Enables output buffer full interrupt to the PM driver
in the host (IRQ11). The interrupt is triggered by a
CR16A write to the HIPMDO Register. The interrupt is
sent according to IRQM and IRQNPOL in the HIIRQC
Register.
0: Interrupt signal low
1: Enables PM output buffer empty interrupt to the
0: Interrupt signal low
1: Enables PM input buffer full interrupt to the CR16A
the HIIRQC Register
driver of the host (IRQ1). The interrupt is triggered
by the CR16A write to the HIKDO Register. The in-
terrupt is sent according to IRQM and IRQNPOL
bits in the HIIRQC Register.
the HIIRQC Register
driver in the host (IRQ12). The interrupt is triggered
by the CR16A write to the HIMDO Register. The in-
terrupt is sent according to IRQM and IRQNPOL
bits in HIIRQC register.
CR16A ICU, for the KBC channel. The interrupt sig-
nal is active when the output buffer is empty (i.e.,
the interrupt signal is set (1) when OBF bit of the
HIKMST Register is cleared).
ICU, for the KBC channel. The interrupt signal is
active when the input buffer is full; the interrupt sig-
nal is set (1) when IBF bit of the HIKMST register is
set.
CR16A ICU, for the PM channel. The interrupt signal
is active when the output buffer is empty (when OBF
bit of the HIPMST register is cleared).
ICU, for the PM channel. The interrupt signal is ac-
tive when the input buffer is empty (when IBF bit in
the HIPMST Register is set).
6
5
IRQM
4
3
IRQ11B IRQ12B IRQ1B
2
1
0