ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 68

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

6.2.13 System Bus Lockout
During power-up or power-down, spurious bus transactions
from the host may occur. To protect the RTC internal regis-
ters from corruption, all inputs are automatically locked out.
The lockout condition is asserted when V
V
6.2.14 Power-Up Detection
When system power is restored after a power failure or
power-off state (V
a delay of 62 ms (minimum) to 125 ms (maximum) after the
RTC switches from battery to system power.
The lockout condition is switched off immediately in the fol-
lowing situations:
6.2.15 Oscillator Activity
The RTC oscillator is active if:
The RTC oscillator is disabled if:
Note: Since the clock multiplier uses the RTC oscillator
If the RTC oscillator becomes inactive, the following fea-
tures will be dysfunctional/disabled:
•
•
•
CCON
If the Divider Chain Control bits, DV0-2, (bits 6-4 in the
CRA Register) specify a normal operation mode (01X or
100), all input signals are enabled immediately upon de-
tection of system voltage above V
When battery voltage is below V
all input signals are enabled immediately upon detection
of system voltage above V
registers at offsets 00h through 0Dh.
If bit 7 (VRT) of the CRD Register is 0, all input signals
are enabled immediately upon detection of system volt-
age above V
V
of the battery voltage, V
V
if V
During power-down (V
drops below V
Thresholds" on page 136 for the value). When this oc-
curs, the oscillator may be disabled and its functional-
ity cannot be guaranteed.
Software wrote 00X to DV2-0 bits of the CRA Register
and V
This disables the oscillator and decreases the power
consumption from the battery connected to the V
pin. When disabling the oscillator, the CMOS RAM is
not affected as long as the battery is present at a cor-
rect voltage level.
Timekeeping
Periodic interrupt
Alarm
APC
CC
BAT
. See section 19-8 on page 136.
CC
as a reference clock, disabling the RTC oscillator
will interfere with the clock multiplier functionality.
See also Section 7.2 on page 76.
power supply is higher than V
power supply is higher than V
CC
is present or not.
is removed (see Section 6.3.1 on page 69).
CCON
CC
=0), the lockout condition continues for
BATMIN
.
BAT
BAT
(see Table 19-8.
Real-Time Clock (RTC) and Advanced Power Control (APC)
CCON
only), the battery voltage
BATDCT
. This also initializes
CCON
CCON
BATMIN
CC
.
and HMR is 1,
, independent
is lower than
, regardless
"Voltage
BAT
68
6.2.16 Interrupt Handling
The RTC has a single Interrupt Request line, IRQ8, which
handles the following three interrupt conditions:
The interrupts are generated (IRQ8 is driven low) if the re-
spective enable bits in the CRB Register are set prior to an
interrupt event occurrence. See also section 5.10 "HOST
INTERRUPTS" on page 52, and section 5.14.14 "IRQ En-
able Register (IRQE)" on page 63.
Reading the CRC Register clears all interrupt flags. Thus,
when multiple interrupts are enabled, the interrupt service
routine should first read and store the CRC Register, and
then deal with all pending interrupts by referring to this
stored status.
If an interrupt is not serviced before a second occurrence of
the same interrupt condition, the second interrupt event is
lost. Figure 6-8 illustrates the interrupt timing in the RTC.
6.2.17 Battery-Backed Register Banks and RAM
The RTC and APC module has three battery-backed regis-
ter banks:
Battery backup power assures information retention during
system power-down.
The memory maps and register content for each of the three
banks is illustrated in Section 6.7 on page 74.
The lower 64-byte locations of the three banks are shared.
The first 14 bytes are used for time and alarm storage and
as control registers. The next 50 bytes are used for general
purpose memory.
Flags (and IRQ) are reset at the conclusion of CRC read
or by reset.
A = Update In Progress (UIP) bit high before
B = Periodic interrupt to update
C = Update to Alarm Interrupt = 30.5 s
P = Period is programmed by RS3-0 of CRA.
UIP bit
of CRA
UF bit
of CRC
PF bit
of CRC
AF bit
of CRC
Periodic interrupt
Alarm interrupt
Update-Ended interrupt.
Bank 0 - General Purpose Register Bank for battery-
backed storage
Bank 1 - RTC Register Bank
Bank 2 - APC Register Bank
= Period (periodic int) / 2 + 244 s
update occurs = 244 s
Figure 6-8. Interrupt/Status Timing
B
244
P/2
30.5
s
P
s
A
C
P/2
www.national.com