ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 57

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

Bit 0 - Host Interrupt Request 1 Control (IRQ1B)
Bit 1 - Host Interrupt Request 12 Control (IRQ12B)
Bit 2 - Host Interrupt Request 11 Control (IRQ11B)
Bits 5-3 - IRQ Mode (IRQM)
Bit 6 - IRQ Negative Polarity (IRQNPOL)
When the IRQ1 signal is configured for direct control by
the firmware (OBFKIE in the HICTRL Register is 0), this
bit directly controls the state of IRQ1 pin. When read,
IRQ1B returns the current value of the IRQ1 pin, which
can be read regardless of the state of OBFKIE.
When the IRQ12 signal is configured for direct control
by the firmware (OBFMIE in the HICTRL Register is 0),
this bit directly controls the state of IRQ12 pin. When
read, IRQ12B returns the current value of the IRQ12
pin, which can be read regardless of the state of
OBFMIE.
When the IRQ11 signal is configured for direct control
by the firmware (PMHIE in the HICTRL Register is 0),
this bit directly controls the state of IRQ11 pin. When
read, IRQ11B returns the current value of the IRQ11
pin, which can be read regardless of the state of PMHIE.
Sets the hardware controlled IRQ signals to work in lev-
el or pulse mode and defines the pulse width in the
pulse modes.
When IRQM = 000
mode. In this mode when IRQNPOL bit below is 0, the
IRQ signals default value is low, and a high level is set
to issue an interrupt (the respective OBF is set).
When IRQM , the host interrupts are in pulse mode.
When IRQNPOL bit below is 0, the IRQ signals default
value is high, and it toggles low to issue an interrupt (i.e.,
when the respective output buffer register is written).
See Table 5-3 for the pulse widths.
0: IRQ signal (IRQ1, IRQ11, IRQ12) polarity is com-
1: When hardware IRQ generation is enabled (when
patible with the standard ISA bus interface.
OBFKIE, OBFMIE or PMHIE for IRQ1, IRQ12 or
IRQ11, respectively in the HICTRL Register are
set), the interrupt output is inverted.
Table 5-3. IRQM Pulse Modes
IRQM
Other
000
001
010
011
100
101
2
2
2
2
2
2
2
, the IRQ signals function in a level
16-cycle Pulse
Level Interrupt
1-cycle Pulse
2-cycle Pulse
4-cycle Pulse
8-cycle Pulse
Reserved
Mode
Host Bus Interface (HBI)
57
Bit 7 - Push Pull Enable (PSPE)
5.12.8 Host Interface KBC Status Register (HIKMST)
The HIKMST Register is a byte wide, read/write register. It
provides the status of the host interface keyboard channel
buffers (DBBIN and DBBOUT) and a means for the
PC87570 to send status bits to the host. This register can
also be read by a host read operation from address 64h.
HIKMST is cleared (00h) on reset.
Bit 0 - Output Buffer Full (OBF)
Bit 1 - Input Buffer Full (IBF)
Bit 2 - Flag 0 (F0)
Bit 3 - A2 Address (A2)
Bits 7-4 - Status Bits 0-3 (ST0-3)
5.12.9 Host Interface Keyboard Data Out Buffer
The HIKDO Register is a byte wide, write only register. It al-
lows the CR16A firmware to write to the DBBOUT Register,
while setting OBF in the HIKMST Register. If enabled, IRQ1
ST3
7
0: IRQ signals (IRQ1, IRQ11 and IRQ12) output driv-
1: IRQ signals drivers are full push-pull drivers.
This bit is a read only bit and is ignored when writing to
this register.
0: Host reads from the KBC channel output buffer
1: KBC channel’s DBBOUT is written by the CR16A
This bit is a read only bit and is ignored when writing to
this register.
0: CR16A reads input buffer (HIKMDI Register)
1: KBC channel’s DBBIN is written by the host (writing
A general-purpose flag that can be set or cleared by the
CR16A firmware.
Holds the value of the HA2 line in the last write operation
of the host to the KBC channel’s input buffer (i.e., indi-
cates HA2 value during write to address 60h or 64h).
This bit is a read only bit and is ignored when writing to
this register.
Four general-purpose flags that can be set or cleared by
the CR16A firmware.
ers are open drain type. Therefore, when an output
logic is 0, the signal is pulled low; when output logic
is 1, the signal is floating and its level is set by the
system. External pull-up resistors should be used.
Therefore, the PC87570 drives the signals for both
low and high levels.
(60h)
(writing to the HIKDO or HIMDO Registers)
to either address 60h, data, or address 64h, con-
trol) T
Register (HIKDO)
ST2
6
ST1
5
ST0
4
A2
3
F0
2
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IBF
1
OBF
0