ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 36

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Note: Any reference to SZCFGn, also applies to the IOCFG Register.
3.3.3
If the BCFG.EWR configuration bit is 1, the BIU uses early
write bus cycles; this allows removal of the RD signal from
the memory device interface. The basic early write bus cy-
cle takes three clock cycles.
The cycle starts at T1, when the data bus is in TRI-STATE
and the address is placed on the address bus. RD is inac-
tive to indicate that this is a write bus cycle; then WR0-1 are
activated.
At the first TIW, or T2 (when there are no TIW cycles), the
data is placed on the data bus and the SELn (or SELIO) is
activated. The bus transaction is terminated at T3, when
Data placed
on D0-15,
SELn: active
TIW
Any reference to SELn, also applies to the SELIO signal.
Early Write Bus Cycle
SZCFGn.WAIT
SZCFGn.HOLD
Internal waits completed
Hold cycles completed
Internal waits corresponding to SZCFGn.WAIT
T
hold
0
0
Hold cycles according to SZCFGn.HOLD
Bus Interface Unit (BIU)
Figure 3-1. Early Write Bus Cycle
begin
T2
T2
T3
T1
end
T1
36
SELn (or SELIO) becomes inactive; then WR0-1 become
inactive and the data bus is put in TRI-STATE. The address
remains valid until T3 is complete.
T
Gn.HOLD or IOCFG.HOLD (may be 0). The address and
data remains valid until the end of the last T
data is put in TRI-STATE in the clock cycle after the last
T
3-2 and 3-3.
If a read bus cycle immediately follows an Early Write bus
cycle, an idle cycle is added between the two.
Data placed on D0-15,
SELn: active
SELn: inactive, WR0-1: inactive,
If SZCFGn.HOLD = 0 data put in TRI-STATE.
hold
hold
Address placed on A0-15,
WR(0-1): activated
Address on A0-15 invalid/changed
Data put in TRI-STATE
or T3 (if no T
clock cycles may follow T3, according to SZCF-
hold
cycle is configured). See Figures 3-1,
SZCFGn.HOLD=0
SZCFGn.WAIT = 0
hold
cycle. The