ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 93

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Receive Idle
In the Receive Idle state, the PS/2 interface waits for input
from any one of the enabled channels. The first of the en-
abled channels to send a start bit is selected for handling by
the shift mechanism. The other two channels are disabled
by forcing “0” on their clock lines.
Start Bit Detection
The start bit is identified by a falling edge on the clock signal
while the data signal is low (0).
If the start bit is identified simultaneously in more then one
channel, one channel is selected for receive, while the other
channel’s transfer is aborted. The channel with the lower
number is selected (i.e., channel 1 has priority over chan-
nels 2 and 3, and channel 2 has priority over channel 3).
The data transfer in the other channels is aborted before 10
data bits have been sent (by forcing the clock signal to 0),
therefore the transmitting PS/2 device re-sends its data
once its interface is enabled again by the firmware. This
mechanism insures that no incoming data is lost.
When the hardware sets (1) the SOT bit and designates the
selected channel in the ACH field, this indicates receipt of
the start bit in the PSTAT register. In addition, if PSIEN.SO-
TIE is set, an interrupt signal to the ICU is set high. The firm-
ware may use this interrupt to start a time-out timer for the
data transfer.
Receive Active
After identifying the start bit, the shift mechanism enters the
“Receive-Active” state. In this state the clock signal of the
selected device (PSCLK1, PSCLK2 or PSCLK3) sets the
data bit rate. On each falling edge of the clock, new data is
sampled on the data signal of the active channel (i.e.,
PSDAT1, PSDAT2 or PSDAT3).
Following the start bit, 8 bits of data are received (clocks 2
through 9), then a parity bit (10th clock) and a stop bit (11th
clock). The stop bit is indicated by a falling edge of the clock
with the data signal high (1). In case the 11th clock is iden-
tified with data low, the receive frame error bit
(PSTAT.RFERR) is set, but the clock is treated as the
STOP bit.
After the parity is received, the shift mechanism checks the
incoming data for parity error. If the number of bits with a
value of 1 in the 8 data bits and the parity bit is even, then
the PSCON.PERR is set indicating a parity error.
CLK
DATA
Start Bit
CLK
1st
Figure 12-5. PS/2 Receive Data Byte Timing
Bit 0
CLK
2nd
PS/2 Interface
93
End of Receive
When the stop-bit is detected, the shift mechanism enters
the “End-Of-Reception” state. In this state:
The shift mechanism stays in this state until it is reset.
Figure 12-5 illustrates the receive byte sequence as it is de-
fined by the PS/2 standard.
12.3.4 Transmit Mode
Transmit Inactive
After enabling the shift mechanism with PSCON.XMT set
(1), transmit mode is entered in the Transmit Inactive state
with all clock signals low and data signals high (PSOSIG =
07h).
At this time, the firmware writes the data to be transmitted
to the PS/2 data register (PSDAT). Then, the data line of the
channel to be transmitted is forced low by the firmware
clearing its data bit (WDAT1, WDAT2 or WDAT3 for chan-
nels 1, 2 or 3, respectively).
Transmit Idle
The Transmit Idle state can be entered by setting the chan-
nel enable bit (CLK1, CLK2 or CLK3 for channel 1, 2 and/or
3, respectively) to enable the channel to be used for trans-
mission. In this state, the shift-mechanism sets the clock of
the enabled channel high (1) while the data line of that
channel is held low and waits for a start bit. When a PS/2
device senses the clock signal high with the data signal low,
it identifies a transmit request from the PC87570.
The two channels not in use are disabled by forcing “0” on
their clock lines.
Start Bit Detection
The start bit is identified by a falling edge on the clock signal
while the data signal is low (0).
The shift mechanism disables all the clock signals by
forcing them low,
It sets the End-Of-Transaction status bit (PSTAT.EOT
=1) and,
If PSTAT.EOTIE is set, it asserts (1) the interrupt sig-
nal to the ICU.
Parity Bit
10th
CLK
Stop Bit
11th
CLK