ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 111

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Mode 3, Dual Independent Timer
Dual Independent Timer mode can be used for a wide vari-
ety of system tasks such as the generation of period system
interrupts, either based on the prescaled clock or external
events on TB. The timer can also toggle the TA pin on un-
derflow allowing the simple generation of a processor-inde-
pendent 50% duty cycle PWM signal on TA. In this mode
TCNT1 counts down, and reloads from TCRA on underflow
while TCNT2 is reloaded from TCRB on underflow.
In this mode the timer is configured to operate as a dual in-
dependent system timer, or dual external event counter. In
addition, timer/counter 1 can generate a 50% duty cycle
PWM signal on the TA pin. The TB pin can be used as an
external event input, or pulse accumulate input, and forms
the clock source to either counter 1 or counter II, as de-
scribed above. Both counters can also be operated from the
prescaled system clock. Figure 14-6 shows a block diagram
of the timer in mode 3.
Timer/counter 1 (TCNT1) counts down at the rate of the se-
lected clock. (See section “Counter Clock Source Select” on
page 108 for additional details). On underflow TCNT1 is re-
Timer 1
Timer 2
Clock
Selector
Clock
Clock
Figure 14-6. Mode 3, Dual Independent Timer
Timer/Counter 1
Timer/Counter 2
Multi-Function 16-Bit Timer (MFT16)
TCNT1
Reload A
Reload B
TCRA
TCNT2
TCRB
Underflow
Underflow
111
loaded from the TCRA register, and counting proceeds. If
enabled, the TA pin toggles on underflow of TCNT1. Soft-
ware can select the initial value of the TA output as either
high or low. See “Timer I/O Functions” on page 113 for ad-
ditional details. In addition, the TAPND interrupt pending
flag is set, and a timer interrupt 1 generated, if the TAIEN bit
is set to 1. (See Section “Timer Interrupts” on page 113 for
detailed information.) Since TA toggles on every underflow,
a 50% duty cycle PWM signal can be generated on TA with-
out requiring any interaction of the user software, and hence
the CPU.
Timer/counter 2 (TCNT2) counts down at the rate of the se-
lected clock. (See Section “Counter Clock Source Select”
on page 108 additional details). On every underflow of
TCNT2 the value contained in the TCRB register is loaded
into TCNT2, and counting proceeds downwards from that
value. In addition, the TDPND interrupt pending flag is set,
and a timer interrupt 2 is generated if the TDIEN bit is set to
1. (See Section 14.4.2 on page 113 for detailed informa-
tion.)
TAPND
TDPND
TDIEN
TAIEN
TAEN
Interrupt 2
Interrupt 1
Timer
Timer
TA
TB