ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 82

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

9.3 ICU REGISTERS
9.3.1
The NMISTAT Register is a byte-wide, read only register. It
holds the status of the PFAIL NMI request. NMISTAT is
cleared each time its contents are read. Non-reserved bits
of NMISTAT are cleared on reset.
Bit 0 - Power Fail Input (PFAIL)
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
7
Interrupt
PFAIL indicates that a falling edge was detected on the
PFAIL pin.
1. To enable the external interrupt, set the pin to its alternate function. When used as I/O port signals the External
2. This interrupt is an OR of the two MIWU outputs. When no WKINTA is an input, disable it by clearing the respec-
3. When in Active mode, you should disable the T0OUT channel of the MIWU, if not required. This saves the need
4. INT10 is the logic OR of EXINT10 after the MIWU and PSINT3. For efficient operation, only one of them should
5. INT11 is the logic OR of EXINT11 after the MIWU and PSINT2. For efficient operation, only one of them should
4
5
interrupt input is forced to 0.
tive bit in WKEN1. When the APC-OFF event is not in use, disable it by clearing the CST2.APCOFFE bit.
to clear the pending bit in the MIWU on each interrupt.
be enabled at a time.
be enabled at a time.
NMI Status Register (NMISTAT)
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
External
Internal
External
Internal
External
Internal
Internal
Internal
Internal
External
Source
Reserved
High Level
High Level
High Level
High Level
High Level
High Level
High Level
Rising Edge
Falling Edge
Falling Edge
High Level
Falling Edge
High Level
High Level
Type
1
Table 9-2. Interrupt Assignment List
External Interrupt 0 (EXINT0)
Host I/F Keyboard/Mouse channel output buffer empty
Host I/F Power Management channel output buffer empty
MIWU WKINTA (PS2, APC-ON, ACCESS.bus wakeup) or WKO24
(APC-OFF
MFT16 interrupt (INT1 OR’ed with INT2)
ADC interrupt
ACCESS.bus interrupt
MIWU WKINTC Internal Keyboard Scan Interrupt (KBSINT)
TWM system tick (T0OUT), through the MIWU
SWIN input
PS/2 interface channel 3 (PSINT3)
External interrupt 10 (EXINT10)
PS/2 interface channel 2 (PSINT2)
External interrupt 11 (EXINT11)
PS/2 shift mechanism (PSINT1)
PS/2 interface channel 1
Host I/F Keyboard/Mouse IBF
Host I/F Power Management IBF
External interrupt 15 (EXINT15)
Interrupt Control Unit (ICU)
PFAIL
0
2
1
)
, through the MIWU
82
9.3.2
The PFAIL Register is a byte-wide read/write register. It pro-
vides control over the early power fail indication NMI. This
register is cleared by hardware on reset.
Bit 0 -PFAIL Trap Enable (EN)
7
An NMI trap is generated when the EN bit is set, and the
PFAIL pin changes its value from high to low. The bit is
cleared by hardware on reset, and whenever the trap
occurs. The EN bit can be set and cleared by
PC87570’s firmware.
Description
Power Fail Control Register (PFAIL)
1
, through the MIWU
Reserved
1
1
1
, through the MIWU
, through the MIWU
, through the MIWU
3
2
PIN
1
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Lowest
Highest
Priority
EN
0