ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 46

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Bit 9 - Post Idle (IPST)
Bit 10 - Preliminary Idle ((IPR)
Bit 11 - Fast Read Enable (FRE)
3.6 USAGE HINTS
The following usage hints will help you configure the BIU to max-
imize PC87570 performance while avoiding contention on the
data bus.
1. In IRE environment, the access time to the internal ROM
2. To avoid data bus contention when a read bus cycle (no
Note: When running boot code (zone 1) in IRE environ-
An idle cycle follows the current bus cycle, when the
next bus cycle is in a different zone
0: No idle cycle inserted
1: Idle cycle inserted
An idle cycle is inserted prior to the current bus cycle,
when this bus cycle is in a new zone
0: No idle cycle inserted
1: Idle cycle inserted
FRE enables fast read bus cycles.
0: Fast read bus cycle disabled. Read bus cycle takes at
1: Fast read bus cycle enabled. Read bus cycle takes
can use zero wait and zero hold cycles, but not fast
reads. Therefore, program SZCFG1 fields as follows:
WAIT=000, HOLD=00, BRE=0, WBE=0, BW=1, FRE=0
(where BRE, WBE, BW and FRE are defaults).
T
cycle in another zone, program IPST and IPRE in the
different memory (I/O) zones as follows:
hold
Environment I/O Expansion
least two clock cycles (i.e., Normal Read bus cycle).
one clock cycle.
ment using the above configuration, performance is
much more efficient than in non-IRE environments.
However, this configuration is not valid in non-IRE
environments.
Non-IRE
clock cycles) in one zone is followed by a read bus
IRE
IRE
Don’t care
Not used
Used
Clear IPST and IPRE
in all zones
Clear IPST and IPRE
in all zones, except
IOCFG.IPST=1
(default)
Clear IPST and IPRE
in all zones, except
SZCFG1.IRE=1
SZCFG.IPST=1 and
IOCFG.IPST=1
(defaults)
.
.
Configuration
Bus Interface Unit (BIU)
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