ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 42

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

www.national.com
3.3.6
When SZCFGn.FRE is 1, the fast read bus cycle is enabled
for zone “n”. The fast read bus cycle takes one clock cycle.
At the beginning of the T1-2 clock cycle the address is
placed on the address bus and SELn and RD are activated.
WR(0-1) are inactive, indicating a read bus cycle. At the end
of the clock cycle, the BIU samples the data. SELn and RD
deactivate in the following clock cycle, unless another read
from the same zone follows. If a write to the same zone fol-
lows, and late write is configured, SELn remains activated.
The address remains valid until the beginning of the clock
cycle after the T1-2 clock cycle.
Fast Read Bus Cycle
Bus State
CLK
A0-18
SELn
D0-7
RD
WR0-1
BST0-2
CLK
A0-18
SELn
D0-7
RD
WR0-1
BST0-2
Figure 3-11. Normal Read Bus Cycle with 2 Internal Waits and 1 Wait on Burst
Figure 3-10. Normal Read Bus Cycle with 0 Wait on Burst
T1
TIW
T1
Bus Interface Unit (BIU)
TIW
T2
In
42
T2B
The fast read bus cycle cannot be extended by adding wait
cycles (SZCFGn.WAIT is ignored during this bus cycle). Ad-
ditionally, hold cycles cannot be added (SZCFGn.HOLD is
also ignored). When a write bus cycle consecutively pre-
cedes a fast read bus cycle, an idle clock cycle is forced be-
tween the two. See Figure 3-12.
When the core attempts to access more bytes (i.e., a word)
than the configured bus width, the transaction is broken up
into “basic” (T1-2) bus cycles.
T2
In
In
TBW
T2B
In