ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 69

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

www.national.com
The upper 64 bytes of bank addresses are utilized as fol-
lows:
Reserved registers and bits should be written using a read-
modify-write method.
The CRA Register selects the active bank according to the
value of bits 6-4 (DV0-2). See Table 6-4.
All register locations are accessed by the RTC Index and
Data Registers (at base address and base address+1). The
Index Register points to the register location being access-
ed, and the Data Register contains the data to be trans-
ferred to or from the location.
In addition to these register banks, an additional 128 bytes
of battery-backed RAM (also called upper RAM) may be ac-
cessed via two levels of addressing, as follows:
There are several ways to lock access to register banks and
RAM. For details, see Section 6.6.4 on page 73.
6.3 RTC REGISTERS
The RTC registers can be accessed at any time during nor-
mal operation mode; i.e.,when V
mended operation range. This access is disabled during
battery-backed operation. The write operation to these reg-
isters is also disabled if bit 7 of the CRD Register is 0 (see
Section 6.3.4 on page 71).
Note: Before attempting to perform any start-up proce-
See Section 6.7 on page 74 for a detailed description of the
memory map for the RTC registers.
This section describes the four RTC Control Registers that
control basic RTC functionality (see Table 6-2). These reg-
isters are shared by all banks.
Additional configuration registers are located at Table 5-2.
"HBI Registers Accessed by CR16A" on page 54 and Table
5-4. "HBI Registers Accessed by Host" on page 61.
Bank 0 supplies an additional 64 bytes of memory-
backed RAM.
Bank 1 uses the upper 64 bytes for functions related
to RTC activity.
Bank 2 uses the upper 64 bytes for functions related
to APC activity.
The first level is the RTC Index and Data registers.
The second level consists of the upper RAM Address
Register, at second level offset 50h of Bank 1, and the
upper RAM Data Register at second level offset 53h of
Bank 1.
dures, make sure to read about bit 7 (VRT) of the
CRD Register (Section 6.3.4 on page 71).
Offset Mnemonic
0Ah
0Bh
0Ch
0Dh
Table 6-2. RTC Control Registers
CRC
CRD
CRA
CRB
RTC Control Register C
RTC Control Register D
RTC Control Register A
RTC Control Register B
Real-Time Clock (RTC) and Advanced Power Control (APC)
Register Name
CC
is within the recom-
69
6.3.1
This register controls bank selection, among other func-
tions.
Note: This register can not be written before reading bit 7
Bits 3-0 - Periodic Interrupt Rate Select (RS3-0)
Bits 6-4 - Divider Chain Control (DV2-0)l
UIP
7
These read/write bits select one of fifteen output taps
from the clock divider chain to control the rate of the peri-
odic interrupt. See Table 6-3 and Figure 6-3 on page 66.
These bits are reset at power-up reset only.
These read/write bits control the configuration of the di-
vider chain for timing generation and register banks se-
lection. See Table 6-4.
These bits are reset at power-up reset only.
Table 6-3. Periodic Interrupt Rate Encoding
of the CRD Register.
RTC Control Register A (CRA)
DV2
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
6
RS
DV1
5
DV0
Periodic Interrupt
4
No interrupts
125.000000
250.000000
500.000000
15.625000
31.250000
62.500000
Rate (ms)
3.906250
7.812500
0.122070
0.244141
0.488281
0.976562
1.953125
3.906250
7.812500
RS3
3
RS2
2
RS1
Divider
Output
1
Chain
10
11
12
13
14
7
8
2
3
4
5
6
7
8
9
RS0
0