ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 47

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

4.0 On-Chip Memory
4.1 INTERNAL RAM
The PC87570 provides a 1024 byte on-chip RAM array.
A 16-bit wide data bus links the CompactRISC CR16A core
and the system RAM array. Each system RAM read or write
operation is one cycle long, and does not include any wait
states.
4.2 INTERNAL ROM
In IRE environment, the PC87570 provides 2 Kbytes of in-
ternal ROM. It is 16 bits wide and can be accessed by byte
or word transactions.
In IRE environment, internal ROM is used as the system’s
Base Memory. In IRD and Dev environments, off-chip Base
Memory replaces the internal ROM to allow development of
software and prototypes.
4.2.1
The SZCFG1 (BIU zone 1 configuration) Register defines
the number of cycles needed to access Base Memory. (See
Section 3.5.3 on page 45 for further details.) The access
time to the ROM can be as fast as zero wait and zero hold
clock cycles, but fast reads cannot be used. To maximize
on-chip ROM performance, see Section 3.6 on page 46.
The access time for internal ROM and off-chip Base Mem-
ory for read operations is the same. This allows cycle-by-cy-
cle compatibility in all the operating environments.
4.2.2
After reset, the on-chip ROM can be accessed at two loca-
tions in the address map, starting from address 10000h and
00000h. The latter location, which is also referred to as the
ROM shadow, holds the same information as that included
in address 10000h
(MCFG.SHOFF=1), access to the ROM shadow is disabled;
only access to the ROM starting from address 10000h is en-
abled. This also enables access to the External Memory.
The PC87570 reset routine should clear the shadow before
attempting to access the External Memory. This should be
done by jumping from the ROM shadow to the main copy
and then setting MCFG.SHOFF.
Access Times
ROM Shadow
.
When the ROM shadow is turned off
On-Chip Memory
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