ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 33
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ADP315PC87570
Manufacturer Part Number
ADP315PC87570
Description
Keyboard and Power Management Controller
Manufacturer
National Semiconductor
Datasheet
1.ADP315PC87570.pdf
(168 pages)
- Current page: 33 of 168
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2.8.3
The I/O expansion protocol permits you to implement I/O
ports in the system, besides those available on-chip, in all
three environments (IRD, IRE and Dev). In IRD and Dev en-
vironments, the I/O expansion protocol enables you to im-
plement the functionality of I/O ports PF, PG and PH using
off-chip external logic. Access to these ports is through the
addresses defined in Chapter A on page 156. The I/O ex-
pansion space is mapped to the address space FB00-
FBFFh. You can use the I/O expansion space as follows:
Addresses in the range FB00h-FB11h may be used to
Accessing I/O Expansion Space
Configuration
1. Legend:
256 K
192 K
128 K
External
56 K
Memory
Disabled
32K x16
64K x16
64 K
32K x8
64K x8
SHBM
X - Alternate function used (I/O port)
Ai - Signal outputs address bit i when the External Memory accessed
Page - Signal outputs the page defined in the Page Register.
0
1
0
PC87570
Address Map
Figure 2-4. External Memory (Zone 0) Address Range
PEALT.1
SHOFF
Table 2-8. External Memory Address Expansion Scheme
0
0
1
0
1
1
1
1
Table 2-7. External Memory Configuration Settings
MCFG
Signal/Pin Connection and Description
MCFG.A15E
A15E
X
0
1
0
1
0
1
1
32 K
EXM16
MCFG.A15E=0
X
0
0
1
1
33
Page18
A18
The protocol accesses the off-chip I/O expansion using I/O
zone of the BIU. The zone select signal (SELIO), address
lines A0-7 and the RD and WR0 signals, are used to inter-
face to the off-chip logic.
X
X
X
SZCFG0.BW
External Memory Address
1
restore GPIO ports PF, PG and PH.
Address FBFEh is used only in Dev environment by
the MCFGSH Register, and must be written after each
write to the MCFG with the same data written to the
MCFG.
Addresses in the range FB30h-FB5Fh are reserved for
development board use.
X
0
0
1
1
Page17
A17
X
X
56 K
WR0-1, RD
WR0, RD
Control
SEL0,
SEL0,
MCFG.A15E=1
X
Interface Signals
Page16
A16
X
X
D0-15
Data
D0-7
X
A15
A15
A15
X
A0-14
A0-15
A0-14
A0-15
Addr
X
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