ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 90

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

12.0 PS/2 Interface
Industry-standard PC-AT-compatible keyboards use a two-
wire, bidirectional TTL interface for data transmission. Sev-
eral vendors also supply PS/2 mouse products and other
pointing devices that employ the same type of interface.
The PC87570 provides three PS/2 data transfer channels.
Each channel has two quasi-bidirectional signals that serve
as direct interfaces to an external keyboard, mouse or any
other PS/2-compatible pointing device. Since the three
channels are identical, the connector ports are interchange-
able.
12.1 FEATURES
12.2 FUNCTIONAL DESCRIPTION
12.2.1 Configuration
The PS/2 interface includes six external signals (PSCLK1,
PSDAT1, PSCLK2, PSDAT2, PSCLK3 and PSDAT3) and
six registers. Channels 1 and 2 always have assigned pins.
A special configuration, shown in Figure 12-1, is required to
also make channel 3 available. See Section 12.5 for register
details.
Three PS/2 channels
Enable/Disable for each of the three channels
Automatic hardware shift mechanism
Hardware support for PS/2 auxiliary device protocol
Processor interrupts at the beginning and end of data
transfer
Optional software-based PS/2 implementation
PS/2 I/F
Registers
RCLK1
WDAT1
RDAT1
CLK1
ENSM
Channel 1
Channel 2
EN1
Channel 3
EN2
EN3
Figure 12-1. PS/2 Interface Functional Diagram
DATI1
DATI2
DATI3
DATO1
DATO2
DATO3
PS/2 Interface
Shift Mechanism
CLKI1
90
CLKI2
CLKI3
12.2.2 Shift Mechanism
The shift mechanism is a proprietary hardware accelerator
that offloads bit level handling of data transfer from the firm-
ware to hardware. It can be enabled to operate in Receive
or Transmit mode, or disabled. Different states in each
mode define the progress of data transfer.
Shift Mechanism Enabled
PS/2 devices’ firmware is significantly simplified when the
shift mechanism is enabled. Using the shift mechanism to
receive or transmit PS/2 data reduces code overhead and
performance requirements from the CompactRISC CR16A
core, and improves the overall interrupt latency of the
PC87570. The shift mechanism includes an 8-bit shift reg-
ister, a state machine and control logic that handle both in-
coming and outgoing data.
Shift Mechanism Disabled
Previous generation keyboard controllers executed the
PS/2 device interface by toggling and monitoring the PS/2
device interface signals via firmware. The PC87570 also
supports this bit toggling mode with polling or interrupt-driv-
en, clock edge detection by disabling the shift mechanism.
The hardware is designed to meet the PS/2 device interface
as defined in “Keyboard and Auxiliary Device Controller
(Types 1 and 2)” - August 1988.
12.2.3 Quasi-Bidirectional Drivers
The quasi-bidirectional drivers have an open drain output
(Q2), an internal pull-up (Q3) and a low impedance pull-
up(Q1). Q2 pulls the signal low whenever the output buffer
data is “0”. The weak pull-up (Q3) is active whenever the
output buffer data is “1” and PSCON.WPUEN is set (1). The
low impedance pull-up is active whenever the PC87570
changes the output data buffer from “0” to “1”, thereby re-
ducing the low to high transition time. The low impedance
pull-up active duration is determined by PSCON.HDRV
field. A schematic description of this output driver appears
in Figure 12-3.
CLKO1
CLKO2
CLKO3
PSDAT1
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PSCLK1