ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 139
ADP315PC87570
Manufacturer Part Number
ADP315PC87570
Description
Keyboard and Power Management Controller
Manufacturer
National Semiconductor
Datasheet
1.ADP315PC87570.pdf
(168 pages)
- Current page: 139 of 168
- Download datasheet (892Kb)
www.national.com
Symbol Figure
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
1
2
3
4
5
6
7
8
9
19-10
19-12
19-10
19-12
19-13
19-13
19-12
19-10 Minimum inactive
19-13
19-13
19-8,
19-8,
19-8,
19-8,
19-8,
19-8
19-8
19-8
19-9
19-9
19-9
19-9 Minimum delay time
19-9 Minimum delay time
19-8
19-8
19-9 D0-15 valid in late
to
to
to
to
to
to
to
Input setup time
D0-15
Input hold time
D0-15
Output valid time
A0-17, BE0,1CBRD,
D0-15
Output valid time
BST0-2
Output
active/inactive time
RD, SEL0-1, SELIO
Output
active/inactive time
WR0-1
time
RD
Output float time
A0-17, D0-15, RD,
SEL0-1,SELIO,WR0-1
Minimum delay time
Output hold time
A0-17, BE0-1, CBRD,
D0-15, RD, SEL0-1,
SELIO
Output hold time
BST0-2, WR0-1
write bus cycles
Description
Before RE CLK
After RE CLK
After RE CLK
After RE CLK
After RE CLK
After RE CLK
After RE RD
After RE CLK
From RE RD to
D0-15 drive
From RE RD to RE
SELn
From RE SELx to FE
SELy
After RE CLK
After RE CLK
Before RE WR0-1
Conditions
Reference
Device Specifications
BIU Output Signals
139
t
t
t
(K + 0.5)
CLK
CLK
CLK
0.5
15 ns
- 4 ns
0 ns
0 ns
0 ns
Min
- 6 ns
V
*
- 5 ns
- 8 ns
0
CC
t
CLK
= 5 V 10%
*
1
0.5
0.5
+ 14 ns
+ 14 ns
14 ns
14 ns
14 ns
Max
*
*
t
t
CLK
CLK
t
t
t
(K + 0.5)
CLK
CLK
CLK
0.5
30 ns
V
- 4 ns
0 ns
0 ns
0 ns
Min
CC
- 8 ns
*
0
- 5 ns
- 8 ns
t
CLK
= 3.3 V
*
1
0.5
0.5
+ 20 ns
+ 17 ns
17 ns
17 ns
17 ns
Max
10%
*
*
t
t
CLK
CLK
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