ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 63

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

Bit 2 - PM Enable (PME)
5.14.13 Function Lock Register (FLR)
The FLR Register provides a lock bit to protect the configu-
ration registers from further change. This lock bit is for any
one of the host interface functions. On reset, the FLR Reg-
ister is cleared, enabling writes to all registers. Writing 1 to
a bit in the register locks the corresponding function. Once
locked, a function cannot be unlocked until reset is applied.
Bit 0 - RTC Channel Configuration Lock (RTCLK)
Bit 1 - KBC Channel Configuration Lock (KBCLK)
Bit 2 - PM Channel Configuration Lock (PMLK)
Bit 7 - Base Address Configuration Lock (SBALK)
SBALK
1: A read or write access by the host to the address
0: PM channel cannot be accessed by the host; i.e.,
1: A read or write access by the host to the address
0: RTC
1: RTC configuration cannot be changed; i.e.,
0: Keyboard channel configuration may be changed;
1: Keyboard
0: PM channel configuration may be changed; i.e.,
1: PM channel configuration cannot be changed; i.e.,
0: Address of the configuration Index and Data Registers
1: Configuration Index and Data Registers address
7
specified by KBCCSAH, KBCCAL generates a chip
select to the KBC channel (HKBCCS).
access to the address specified in PMCSAH, PMC-
SAL does not generate a chip select.
specified by PMCSAH, PMCAL generates a chip se-
lect to the PM channel (HPMCS).
RTCCSAH and RTCCSAL Registers and RTCE in
the FER Register may be written.
RTCCSAH and RTCCSAL Registers and RTCE in
the FER Register become read only. Any data writ-
ten to them is ignored.
i.e., KBCCSAH and KBCCSAL Registers and
KBCE in the FER Register may be written.
changed; i.e., KBCCSAH and KBCCSAL Registers
and KBCE in the FER Register become read only.
Any data written to them is ignored.
PMCSAH and PMCSAL Registers and PME in the
FER Register may be written.
PMCSAH and PMCSAL Registers and PME in the
FER Register become read only. Any data written
to them is ignored.
may be changed; i.e., SBAL and SBAH may be written.
cannot be changed; i.e., SBAL and SBAH become
read only. Any data written to them is ignored.
6
configuration
Reserved
5
channel
4
may
configuration
3
PMLK KBCLK RTCLK
be
2
changed;
1
cannot
Host Bus Interface (HBI)
0
i.e.,
be
63
5.14.14 IRQ Enable Register (IRQE)
The IRQE Register allows the host to enable the interrupt
signals. On reset, this register is set according to the value
of HDEN. If HDEN=0, it is cleared, disabling all interrupts by
placing the pins in TRI-STATE. If HDEN=1, non-reserved
bits in the IRQE Register are set to enable the interrupts.
For a description of the various IRQ modes, see Section
5.10.
Bit 0 - Interrupt Request 1 Enable (IRQ1E)
Bit 1 - Interrupt Request 12 Enable (IRQ12E)
Bit 2 - Interrupt Request 11 Enable (IRQ11E)
Bit 3 - Interrupt Request 8 Enable (IRQ8E)
7
0: IRQ1 is in TRI-STATE
1: IRQ1 signal is active, according to the mode select-
0: IRQ12 is in TRI-STATE
1: IRQ12 signal is active, according to the mode se-
0: IRQ11 is in TRI-STATE
1: IRQ11 signal is active, according to the mode se-
0: IRQ8 is in TRI-STATE
1: IRQ8 signal is active, according to the mode select-
ed.
lected.
lected.
ed.
Reserved
6
5
4
IRQ8E IRQ11E IRQ12E IRQ1E
3
2
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