ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 22

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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CLK
D15-0
DA3-0
ENV1,0
EXINT0
EXINT10
EXINT11
EXINT15
GA20
GND
HA18-0
HAEN
HD7-0
HDEN
HIOCHRDY
HIOR
Signal
138-123
160-152
160-pin
22, 24,
60, 99,
93, 94
88-85
20-13
10-1,
146
101
144
97
58
69
59
62
70
11
12
Pin Number
103, 104
152-137
66, 109,
174-166
176-pin
24, 26,
98-95
22-15
12-3,
107
160
111
158
64
75
65
68
76
13
14
Signal/Pin Connection and Description
-
TTL
-
STRAP
TTL
-
N/A
TTL
TTL
TTL
STRAP
-
TTL
Input
Buffer Type
22
CM
CM
ANOUT
-
-
CM
N/A
-
-
CMHD2
-
OD2
-
Output
PC87570 internal clock (On-chip Clock Multi-
plier output). Available in all environments. For
IRE environment, set MCFG.CLKOE=1. See
Table 2-5 on page 27.
CR16A Memory Data bus bits 15 through 0.
Digital to Analog Converter Output.
Environment select strap pins.These pins define
if the device environment, IRE, IRD or DEV.
They are sampled on power-up reset. See Sec-
tion 2.4 on page 26.
External Interrupt Inputs 0, 10, 11, 15. Interrupt
signals for general purpose use. These interrupt
signals are asynchronous. See Table 9-2 on
page 82.
Gate A20 output. See Section 5.11.6 on page
54.
Ground for both on-chip logic, output drivers
and back-up battery circuit. See Figure 19-1 on
page 132 for details on connections with
AGND. See also Figure 16-4 on page 125 and
Figure 17-2 on page 129.
Host Address lines inputs to address registers
in the KBC, PM, RTC/APC and the configura-
tion registers. See Section 5.5.2 on page 50
and Section 5.4.3 on page 50. See also
“HPWRON” pin description below.
Host Address Enable should be low during
HIORD and HIOWR bus transactions, otherwise
the bus transaction is ignored. Refer to Section
19.5.4 on page 150.
Host Data. Bi-directional data bus used to inter-
face the PC87570 to the peripheral data bus of
the host. Refer to Section 19.5.4 on page 150.
Host Device Enable, strap pin.
When pulled high during power-up reset, con-
figures the Host device (host interface and
RTC) to be enabled as default after each reset.
When low during power-up reset, the mother-
board PnP protocol must be used to enable the
host access to these devices after each reset.
See Section 2.4.2 on page 26 and Section
5.11.5 on page 54.
Host I/O Channel Ready. An open drain output
that enables extending the host access. This is
used for handling the dual ported access to the
CMOS RAM and to share memory with the
host. See “HRMS” and “HPWRON” pins
description below.
Host I/O Read. Active-low input that signals an
I/O data read by the host processor.
Function