ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 76

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

7.0 High Frequency Clock Generator
The HFCG generates the high-frequency clock based on
the system’s 32 KHz clock signal. It is controlled by the
PMC.
7.1 FEATURES
.
7.2.1
To change the HFCG frequency, load the HFCGN and
HFCGM variables with new values. The HFCGM variable is
loaded in two parts by writing to the HFCGML and HFCG-
MH registers.
Load the new setting (HFCGN and HFCGM values, simul-
taneously) into the frequency multiplier. The core writes the
new variables into a data input buffer. Then, a command
loads the new values into the frequency multiplier.
To set a new clock frequency:
1. Write the HFCGN value.
2. Write the HFCGML value.
3. Write the HFCGMH value.
4. Set HFCGCTRL.LOAD = 1.
When the new HFCGML, HFCGMH and HFCGN values are
loaded, the HFCG holds the output clock low until the fre-
quency multiplier locks onto the target frequency, and the
new frequency stabilizes. This automatic locking process
can take up to several milliseconds to complete.
Frequencies within the range of 4.00 to 10.00 are valid. See
Table 7-1 for a sampling of selected frequencies and their
corresponding HFCGM and HFCGN values.
•
•
Programmable frequency multiplier for a wide range of
output frequencies
On power-up and WATCHDOG reset, 4 MHz default fre-
quency is set
(HFCG)
Setting Clock Frequency
From PMC
To PMC
32 KHz CLK
CLK
High Frequency Clock Generator (HFCG)
Figure 7-1. HFCG Schematic Diagram
HFCG Enable
Frequency
Multiplier
76
7.2 FUNCTIONAL DESCRIPTION
The HFCG programmable frequency multiplier creates a
high-frequency output clock from a 32.768 KHz input clock.
A 5-bit and 14-bit variable define the output clock frequency.
The software changes the generated frequency by writing
new values to a buffer and enabling the frequency setting.
Either a normal or fast clock setting may be used. During a
frequency change, the CLK output is low, to prevent the
system from using a non-stable clock.
The HFCG is designed to be tightly coupled with the PMC.
The HFCG Enable signal coming from the PMC is input to
the HFCG, enabling or disabling clock generation in Idle
mode. The PMC enables the CLK for the PC87570 in Active
mode.
Figure 7-1 shows the HFCG blocks, and the operating en-
vironment.
4.00 (default)
Freq
Table 7-1. Frequencies of Selected Settings
14
14
10.00
1. This value is referred to as t
5.00
6.00
7.00
8.00
9.00
1
the AC specifications.
(MHz) HFCGMH
Data Out
Control
Data In
Status
and
0Ah
0Bh
04h
05h
07h
08h
09h
Peripheral Bus
HFCGML
8
BBh
ECh
C5h
F6h
27h
58h
89h
8
CLKINTnom
HFCGN
www.national.com
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
in