TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 88

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.5
Interrupts
Table 7-3 List of Interrupt Sources
7.5.1.6
No.
40
41
42
43
44
45
46
47
48
49
INTTB7
INTTB8
INTTB9
INTCAP20
INTCAP21
INTCAP30
INTCAP31
INTCAP40
INTCAP41
INTAD
recognizes interrupt signals in "High" level as interrupt. Interrupt signals directly sent from peripheral func-
tions to the CPU are configured to output "High" to indicate an interrupt request.
requests from peripheral functions are set as rising-edge or falling-edge triggered. Interrupt requests from
interrupt pins can be set as level-sensitive ("High" or "Low") or edge-triggered (rising or falling).
also required. Enable the CGIMCGx<INTxEN> bit and specify the active level in the CGIMCGx<EMCGx>
bits. You must set the active level for interrupt requests from each peripheral function as shown in Table
7-3.
The active level indicates which change in signal of an interrupt source triggers an interrupt. The CPU
Active level is set to the clock generator for interrupts which can be a trigger to release standby. Interrupt
If an interrupt source is used for clearing a standby mode, setting the relevant clock generator register is
An interrupt request detected by the clock generator is notified to the CPU with a signal in "High" level.
Active level
Note:For the CEC reception/transmission, remote control signal reception and real time clock inter-
rupts, set the <INTxEN> bit to "1" and specify the active level, even when they are not used for
clearing a standby mode.
16-bit TMRB match detection 7
16-bit TMRB match detection 8
16-bit TMRB match detection 9
16-bit TMRB input capture 20
16-bit TMRB input capture 21
16-bit TMRB input capture 30
16-bit TMRB input capture 31
16-bit TMRB input capture 40
16-bit TMRB input capture 41
A/D conversion completion
Interrupt Source
Page 68
(Clearing standby)
active level
TMPM330FDFG/FYFG/FWFG
CG interrupt mode
control register