TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 16

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12. Consumer Electronics Control (CEC)
viii
11.6 Data Transfer Procedure in the I2C Bus ModeI2C.............................................................288
11.7 Control register of SIO mode..............................................................................................297
11.8 Control in SIO mode............................................................................................................303
12.1 Outline.................................................................................................................................311
12.2 Block Diagram.....................................................................................................................312
12.3 Registers..............................................................................................................................313
12.4 Operations............................................................................................................................331
11.5.9
11.5.10
11.5.11
11.5.12
11.5.13
11.5.14
11.5.15
11.5.16
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.7.6
11.8.1
11.8.2
12.1.1
12.1.2
12.1.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
12.3.9
12.3.10
12.3.11
12.3.12
12.3.13
12.3.14
12.4.1
12.4.2
11.6.2.1
11.6.2.2
11.6.3.1
11.6.3.2
11.8.1.1
11.8.1.2
11.8.2.1
11.8.2.2
11.8.2.3
11.8.2.4
12.4.2.1
12.4.2.2
12.4.2.3
12.4.2.4
Interrupt Service Request and Release..........................................................................................................................285
Device Initialization.......................................................................................................................................................288
Generating the Start Condition and a Slave Address.....................................................................................................288
Transferring a Data Word..............................................................................................................................................290
Generating the Stop Condition......................................................................................................................................295
Restart Procedure...........................................................................................................................................................295
SBIxCR0(control register 0)..........................................................................................................................................297
SBIxCR1(Control register 1).........................................................................................................................................298
SBIxDBR (Data buffer register)....................................................................................................................................299
SBIxCR2(Control register 2).........................................................................................................................................300
SBIxSR (Status Register)...............................................................................................................................................301
SBIxBR0 (Baud rate register 0).....................................................................................................................................302
Serial Clock....................................................................................................................................................................303
Transfer Modes..............................................................................................................................................................305
Reception.......................................................................................................................................................................311
Transmission..................................................................................................................................................................311
Precautions.....................................................................................................................................................................311
Register List...................................................................................................................................................................313
CECEN (CEC Enable Register)....................................................................................................................................314
CECADD (Logical Address Register )..........................................................................................................................315
CECRESET (Software Reset Register).........................................................................................................................316
CECREN (Receive Enable Register).............................................................................................................................317
CECRBUF (Receive Buffer Register)...........................................................................................................................318
CECRCR1 (Receive Control Register 1).......................................................................................................................319
CECRCR2 (Receive Control Register 2).......................................................................................................................321
CECRCR3 (Receive Control Register 3 )......................................................................................................................323
Sampling clock..............................................................................................................................................................331
Reception.......................................................................................................................................................................331
Arbitration Lost Detection Monitor.............................................................................................................................285
Slave Address Match Detection Monitor.....................................................................................................................287
General-call Detection Monitor...................................................................................................................................287
Last Received Bit Monitor...........................................................................................................................................287
Data Buffer Register (SBIxDBR)................................................................................................................................287
Baud Rate Register (SBIxBR0)...................................................................................................................................287
Software Reset.............................................................................................................................................................287
CECTEN (Transmit Enable Register).........................................................................................................................325
CECTBUF (Transmit Buffer Register)........................................................................................................................326
CECTCR (Transmit Control Register)........................................................................................................................327
CECRSTAT (Receive Interrupt Status Register)........................................................................................................329
CECTSTAT (Transmit Interrupt Status Register).......................................................................................................330
Master mode
Slave mode
Master mode (<MST> = "1")
Slave mode (<MST> = "0")
Clock source
Shift Edge
8-bit transmit mode
8-bit receive mode
8-bit transmit/receive mode
Data retention time of the last bit at the end of transmission
Basic Operation
Preconfiguration
Enabling Reception
Detecting Error Interrupt