TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 349

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.3.13
31-7
6
5
4
3
2
1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
CECRIWAV
CECRIOR
CECRIACK
CECRIMIN
CECRIMAX
CECRISTA
CECRIEND
Bit Symbol
Note:Writing to this bit is ignored.
CECRSTAT (Receive Interrupt Status Register)
31
23
15
0
0
0
7
0
-
-
-
-
R
R
R
R
R
R
R
R
Type
CECRIWAV
30
22
14
0
0
0
6
0
Read as 0.
Interrupt flag
0: No wave form error
1: Wave form error
Indicates that waveform error is detected.
The error occurs when waveform error detection is enabled in CECRCR3 <CECWAVEN>.
Interrupt flag
0: No receive buffer overrun
1:Receive buffer overrun
Indicates the receive buffer receives next data before reading the data that had already been set.
Interrupt flag
0: No ACK collision
1: ACK collision
Indicates "0" is detected after the specified time to output ACK bit "0".
Interrupt flag
0: No minimum cycle error
1:Minimum cycle error
Indicates one bit cycle is shorter than the minimum cycle error detection time specified in
CECRCR1<CECMIN>.
Interrupt flag
0: No maximum cycle error
1: Maximum cycle error
Indicates one bit cycle is longer than the maximum cycle error detection time specified in
CECRCR1<CECMAX>.
Interrupt flag
0: No start bit detection
1: Start bit detection
Indicates a start bit is detected.
Interrupt flag
0: Not one byte data reception completed
1: Completion of 1 byte data reception
Indicates 1 byte of data reception is completed.
-
-
-
CECRIOR
29
21
13
0
0
0
5
0
-
-
-
CECRIACK
Page 329
28
20
12
0
0
0
4
0
-
-
-
CECRIMIN
27
19
11
Function
0
0
0
3
0
-
-
-
CECRIMAX
26
18
10
0
0
0
2
0
-
-
-
TMPM330FDFG/FYFG/FWFG
CECRISTA
25
17
0
0
9
0
1
0
-
-
-
CECRIEND
24
16
0
0
8
0
0
0
-
-
-