TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 344

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TMPM330FWFG

Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM330FWFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM330FWFG
Manufacturer:
Toshiba
Quantity:
10 000
12.3
Registers
<CECWAV3>: This setting is enabled when the <CECWAVEN> bit is set to "1".
<CECWAV2>/
<CECWAV1>:
<CECWAV0>: This setting is enabled when the <CECWAVEN> bit is set to "1".
Note:Changing the configurations during reception may harm its proper operation. Before the change, set
CECREN <CECREN> to disable the reception and read the <CECREN> bit to ensure that the operation
is stopped.
By setting these bits, an error is detected if rising edge of the received waveform comes later than that of proper logical "0".
Base time is 56/fs (approx. 1.709ms). Enables to specify it between the ranges 0 to +7/fs by the unit of 1/fs.
The received waveform is considered to be an error if a rising edge is not detected from the start point of the bit to the value
specified in <CECWAV3>.
This setting is enabled when the <CECWAVEN> bit is set to "1".
By setting these bits, an error is detected if rising edge of the received waveform comes faster than logical "0" and later than
that of proper logical "1".
Base time for <CECWAV1> bit is 26/fs (approx. 0.793ms). Enables to specify it between the ranges 0 to +7/fs by the unit of 1/
fs.
Base time for <CECWAV2> bit is 43/fs (approx.1.312ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/
fs.
If a rising edge is detected during <CECWAV2> bit and <CECWAV1> bit setting, an error occurs.
By setting these bits, an error is detected if rising edge of the received waveform comes faster than that of proper logical "1".
Base time is 13/fs (approx. 0.396ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/fs.
The received waveform is considered to be an error if a rising edge is not detected from a start point of the bit to the value
specified in <CECWAV0>.
Page 324
TMPM330FDFG/FYFG/FWFG

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