TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 119

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

31
30-28
27-25
24
23
22-20
19-17
16
15
14-12
11-9
8
7
6-4
3-2
1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
7.6.3.4
Note 1: <EMSTx> is effective only when <EMCGx[2:0]> is set to "100" for both rising and falling edge. The active level
Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously
−
−
−
−
−
−
−
−
−
−
−
−
−
EMCGC[2:0]
EMSTC[1:0]
−
INTCEN
Bit Symbol
used for the reset of standby can be checked by referring <EMSTx>. If interrupts are cleared with the CGICRCG
register, <EMSTx> is also cleared.
is prohibited.
CGIMCGD(CG Interrupt Mode Control Register D)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R
R/W
Type
30
22
14
0
0
0
6
0
Read as 0.
Write any value.
Read as 0.
Write as 0.
Read as 0.
Write any value.
Read as 0.
Write as 0.
Read as 0.
Write any value.
Read as 0.
Write as 0.
Read as 0.
active level setting of INTCECTX standby clear request.
Set it as shown below.
011: Rising edge
active level of INTCECTX standby clear request.
00: −
01: Rising edge
10: Falling edge
11: Both edges
Reads as undefined.
INTCECTX Clear input
0:Disable
1: Enable
-
-
-
EMCGC
29
21
13
1
1
1
5
1
-
-
-
Page 99
28
20
12
0
0
0
4
0
-
-
-
27
19
11
Function
0
0
0
3
0
-
-
-
EMSTC
26
18
10
0
0
0
2
0
-
-
-
TMPM330FDFG/FYFG/FWFG
Undefined
25
17
0
0
9
0
1
-
-
-
-
INTCEN
24
16
0
0
8
0
0
0
-
-
-